Method of forming gate electrode with titanium polycide...

Details Method of forming gate electrode with titanium polycide... Method of forming gate electrode with titanium polycide...

1999-11-05

2001-07-03

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000, C438S769000, C438S770000

Reexamination Certificate

active

06255206

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a gate electrode with a titanium polycide structure in which a titanium silicide layer is formed on a polysilicon layer.
2. Description of the Related Art
In general, a gate electrode of a MOS transistor has been formed of a doped polysilicon layer. However, as semiconductor device is highly integrated, the line widths of a gate electrode and other patterns become fine. Recently, the line width is reduced below 0.15 &mgr;m. Therefore, there are problems that it is difficult to apply the doped polysilicon layer to a gate electrode material in a high speed device, since the doped polysilicon layer has a high resistivity. These problems are also growing more and more serious as the high integration of the semiconductor. To overcome these problems, a gate electrode with a titanium polycide structure in which a titanium silicide layer is formed on the polysilicon layer, is mainly applied to a semiconductor device over 1GDRAM.
FIG. 1A
to
FIG. 1E
are cross sectional views describing a method of forming a gate electrode with a titanium polycide structure according to a prior art.
Referring to
FIG. 1A
, a gate insulating layer
12
is formed on a semiconductor substrate
11
by thermal growth or deposition method and a doped polysilicon layer
13
is formed thereon. Next, a titanium silicide(TiSi
x
) layer
14
of an amorphous phase is deposited on the polysilicon layer
13
by physical vapor deposition(PVD) using TiSi
x
target, as shown in FIG.
1
B. Rapid thermal processing(RTP) is then performed at a selected temperature for several seconds, to transform the TiSi
x
layer
14
of the amorphous phase into a TiSi
2
layer
14
a
of a crystalline phase, as shown in FIG.
1
C.
Referring to
FIG. 1D
, a mask insulating layer
15
is formed in the shape of a gate electrode on the TiSi
2
layer
14
a
, for a conventional self-aligned contact(SAC) process which will be performed after. Here, the mask insulating layer
15
is formed of an oxide layer or a nitride layer. Thereafter, the TiSi
2
layer
14
a
and the polysilicon layer
13
are etched using the mask insulating layer
15
as an etch mask, to form a gate electrode
100
.
Referring to
FIG. 1E
, for removing damage due to the etching process and recovering the reliability of the gate insulating layer
12
, the structure of
FIG. 1D
is oxidized by re-oxidation process to form an oxide layer
16
on the side wall of the gate electrode
100
and on the surface of the substrate
11
. The re-oxidation process is generally performed at the temperature 800° C. or more.
However, when performing the re-oxidation process, the side wall of the TiSi
2
layer
14
a
of the gate electrode
100
is excessively oxidized due to the fast oxidation rate of the TiSi
2
layer
14
a
, thereby reducing the line width of the TiSi
2
layer
14
a
and aggravating the morphology of the gate electrode
100
, as shown in FIG.
1
E. Therefore, it is difficult to perform ion-implantation for forming a source and a drain subsequently. Furthermore, the resistivity of the gate electrode increases, thereby deteriorating the reliability of a device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to a method of forming a gate electrode with a titanium polycide structure which can prevent abnormal oxidation of the gate electrode and reduce the resistivity of the gate electrode when performing a re-oxidation process, for solving the problems in the conventional art.
To accomplish this above object, according to the present invention, a gate insulating layer, a polysilicon layer and a titanium silicide layer are formed on a semiconductor substrate, in sequence. A mask insulating layer is then formed in the shape of a gate electrode on the titanium silicide layer. Next, the titanium silicide layer and the polysilicon layer are etched using the mask as an etch mask insulating layer to form a gate electrode. Thereafter, the substrate is oxidized using reoxidation process to form an oxide layer with a uniform thickness on the side wall of the gate electrode and on the surface of the substrate. Here, the re-oxidation process is performed at the temperature of 750° C. or less using dry oxidation.
Furthermore, the re-oxidation process is performed at the temperature of 700 to 750° C. and the oxide layer is formed to the thickness of 30 to 60 Å, preferably, about 50 Å.
Additional object, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.


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