Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-20
2001-01-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000
Reexamination Certificate
active
06180465
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to integrated circuit manufacture; and more particularly to a method of manufacture and a structure in which a gate conductor is formed in a scaled device that has a width less than that obtainable by a minimum lithographic feature size.
2. Description of the Related Art
The structure and the various components, or features, of a metal oxide semiconductor (MOS) devices are generally well known. A MOS transistor typically includes a substrate material onto which a gate dielectric and a patterned gate conductor are formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source and drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs N-type junctions placed into a P-type substrate. Conversely, a typical p-channel MOS transistor comprises P-type junctions placed into an N-type substrate. The substrate comprises an entire monolithic silicon wafer, of which, a portion of the substrate known as a “well” exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both N-type and P-type transistors (i.e., Complementary MOS, “CMOS”) are needed.
A common trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductors, source and drain junctions, and interconnects to the junctions must be made as small as possible. Many modern day processes employ features which have as small as 0.20 microns critical dimensions. As feature sizes decrease, the size of the resulting transistors as well as the interconnections between transistors also decrease. Smaller transistor size allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single and relatively small die area. Further, smaller transistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation. These features in combination allow for higher speed integrated circuits to be constructed that have greater processing capabilities and that produce less heat.
The benefits of high-density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the higher resolutions needed for submicron features. To some extent, wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
Many other techniques are often used to achieve a higher density circuit. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot, in all instances, offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects (“SCE”) generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive subthreshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection (“HCI”). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric fields give rise to so called hot carriers and the injection of these carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since these carriers can become trapped and skew the turn-on threshold voltage of the ensuing transistor. In view of these considerations, certain scaling limits are being reached.
Additional problems relate to reducing the channel length in scaled transistors. Because lithography equipment is limited to a smallest dimension, the channel length cannot be made shorter than the smallest dimension. Such channel length limitation has heretofore provided a lower limit on the shortest obtainable channel length. Thus, there exists a need in the art for a method of forming devices that have channel lengths shorter than the limits placed thereupon by lithography equipment.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the transistor formation process according to the present invention in which gate conductors are formed which have widths less than the smallest dimension available using lithography. In such method of formation, a source/drain region may be first doped at a desired level. Then, a dielectric layer is blanked formed across the surface of the substrate and etched to form a channel opening above the source drain region. A nitride layer is then formed on the substrate and partially removed to leave spacers on inner sidewalls of the dielectric layer in the channel opening.
The source/drain region is then removed in an etching step to expose an undoped portion of the active region. Such etching step segregates the source/drain region into a source and a drain. A Vt region may then be formed in the channel region upon the active region. Thereafter, a gate dielectric is formed that includes a thin nitrogen bearing oxide layer and a high K layer. A gate conductor is then formed to create formation of the gate. The oxide layer on both sides of the gate is then partially or fully removed to expose the source and drain. Additional doping and/or annealing may be performed to create formation of the source, drain and LDD regions.
Creation of a transistor in this fashion allows the gate conductor to have a width less than that obtainable in a lithography step. Further, when the gate dielectric extends below a lower portion of the source and drain, short channel effects are reduced or eliminated.
These and other aspects of the present invention will become apparent with further reference to the drawings and specification which follow.
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Gardner Mark I.
Nguyen Thien Tung
Advanced Micro Devices
Garlick Bruce
Hack Jonathan
Harrison James
Niebling John F.
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