Method of forming four transistor SRAM cell having a resistor

Details Method of forming four transistor SRAM cell having a resistor Method of forming four transistor SRAM cell having a resistor

1999-03-05

2001-10-02

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S382000

Reexamination Certificate

active

06297083

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to fabricating Integrated circuits and, more specifically, to a static random access memory (SRAM) integrated circuit with a reduced cell size and the fabrication method.
BACKGROUND OF THE INVENTION
With the demand for higher levels of integration of semiconductor chips, such as silicon semiconductor chips, there is a need for greater density and a demand to reduce the amount of silicon used for each of the circuits. This is especially the case with a SRAM, either on a microprocessor integrated circuit chip, of which a large portion of the silicon is a SRAM, or as a separate chip. For increased performance of future microprocessor, the storage capacity of the SRAM must increase thereby requiring a larger portion of the silicon of the microprocessor as the SRAM or a larger separate SRAM chip.
A 1-bit storage cell in a SRAM consists of a simple latch circuit with two stable operating points or nodes. Depending on the preserved state of a two-inventor latch circuit, the bit of data being held in the cell will be interpreted either as a logic “0” or as a logic “1”. To access the data in the cell via a bit line, a switch is controlled by a corresponding word line carrying a row address selection signal. Two complementary access switches are used to connect the 1-bit SRAM cell to the complementary bit lines. A field effect transistor (FET) SRAM cell consists of two cross-coupled inventors and two access transistors. The load devices may be polysilicon resistors, depletion-type N-type FETs, or P-type FETs depending on the type of SRAM cell. Pass gates acting as data access switches are enhancement-type N-type FETs. Of those load devices, the use of resistive-load inventors with polysilicon resistors in the latch structure results in a significantly more compact cell size, compared with the other alternative described, because it reduces the cell size to four transistors in contrast to six transistors of the other alternative. However, creating a polysilicon load resistor is quite difficult and expensive from manufacturing standpoint in that, not only is a critical mask required for the polysilicon load resistor, but another critical mask is required for the contact to the load resistor, conventionally called a quasi-buried contact (QBC). In addition, a care must be taken to isolate the polysilicon load resistor. Although a load resistor takes less layout space than a FET, the resistor still takes up a significant amount of space. Further special implants and other special processing is usually required in fabricating the polysilicon load resistor.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an integrated circuit fabrication method which reduces layout area of a SRAM with resistive loads.
Another object of present invention is to provide an integrated circuit fabrication method in which critical masks and special implants are not required in manufacturing a SRAM with resistive load.
A further object of present invention is to provide an integrated circuit fabrication method which reduces the level of manufacturing difficulty and lowers the expense in the manufacture of SRAMs with resistive loads.
In accordance with the present invention, a load resistor of a SRAM is fabricated by using amorphous (&agr;) silicon which is sandwiched between two metals which function as barrier metals and which is disposed adjacent a conductive via between a pair of conductive line. The fabrication method comprises the steps of: forming a conventional FET with a level of metallization of a first conductive line; forming an interlevel insulating layer on the conductive line; forming a via opening in the insulation having a bottom adjacent the conductive line; forming a resistor comprising a conductive material in the via opening and an amorphous (&agr;) silicon layer adjacent each other and a plurality of barrier metal layers, at least one being in contact with &agr;-silicon layer and at least one being in contact within the conductive material; and forming a level of metallization of a second conductive line, said &agr;-silicon resistor being between the first and second conductive line.


REFERENCES:
patent: 4924295 (1990-05-01), Kuecher
patent: 5045149 (1991-09-01), Nulty
patent: 5120679 (1992-06-01), Boardman et al.
patent: 5182225 (1993-01-01), Matthews
patent: 5290734 (1994-03-01), Boardman et al.
patent: 5328865 (1994-07-01), Boardman et al.
patent: 5530418 (1996-06-01), Hsu et al.
patent: 5882997 (1999-03-01), Sur, Jr. et al.

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