Semiconductor memory device having high-concentration region...

Details Semiconductor memory device having high-concentration region... Semiconductor memory device having high-concentration region...

1997-11-10

2001-05-22

Whitehead, Jr., Carl (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C257S318000, C257S319000, C257S320000, C257S321000, C257S322000, C257S336000, C257S344000, C257S408000, C257S900000

Reexamination Certificate

active

06236085

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority of prior Japanese Patent Applications No. H. 8-299052 filed on Nov. 11, 1996 and No. H. 8-299053 filed on Nov. 11, 1996, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a MIS (Metal Insulator Semiconductor) transistor type nonvolatile semiconductor memory device having a two-layer electrode structure made up of a floating gate and a control gate. In particular, the invention can be preferably realized as a MOS (Metal Oxide Semiconductor) transistor type nonvolatile semiconductor memory device.
2. Description of Related Art
In nonvolatile semiconductor memory devices such as EEPROMs and flash memories, high-concentration P-type regions called P-pockets are formed around electric-field moderating layers and the source and the drain to increase writing speed by increasing the efficiency of formation of hot carriers during writing operation.
A conventional nonvolatile semiconductor memory device is manufactured by the steps illustrated in
FIGS. 12A through 12D
. Specifically, a floating gate
3
is formed on a P-well region
1
formed in a substrate, with a first gate insulating film
2
therebetween. Then, a control gate
5
is formed on the floating gate
3
, with a second gate insulting film
4
therebetween. After that, an oxide film
6
is formed to a suitable thickness and N-type impurity is ion-implanted to form a source
6
a
and a drain
6
b
, as shown in FIG.
12
B. Also, an N-type impurity is diagonally ion-implanted to form electric-field moderating layers
7
, as shown in FIG.
12
C. Next, boron is diagonally ion-implanted and high-concentration P-type regions
8
a
,
8
b
called P-pockets are formed around the electric-field moderating layers
7
and next to the lower parts of the source
6
a
and the drain
6
b
, as shown in FIG.
12
D.
However, when a nonvolatile semiconductor memory device is manufactured in the way described above, the high-concentration P-type region
8
b
is formed in contact with the bottom surface of the electric-field moderating layer
7
and the lower part of the drain
6
b
. As a result, the width of a depletion layer formed between the N-type regions of the electric-field moderating layer
7
and the drain
6
b
and the high-concentration P-type region
8
b
becomes narrow and the diffusion capacitance of this P-N junction increases. This increase in capacitance lengthens the time required for charging and discharging of charges, and consequently the switching speed of when reading operation of the semiconductor memory device is carried out is made slow.
It is therefore a first object of the invention to provide a semiconductor memory device and a method for manufacturing the same with which it is possible to suppress a delay in switching speed while quickening writing speed by eliminating the influence of a high-concentration region of the opposite conductive type formed adjacent to the bottom surface of an electric-field moderating layer and lower parts of source and drain layers.
One example of known nonvolatile memories in which electrical overwriting and erasing are possible is a flash memory. Generally, as shown in
FIG. 18
, a flash memory
100
consists of a large number of bits arrayed in a matrix. When reading and writing operations are carried out in this kind of flash memory
100
, a voltage acts on the terminals of bits other than the selected bit (hereinafter referred to as non-selected bits) as well on the selected bit. Consequently, it sometimes happens that in non-selected bits charge is exchanged between the charge holding part of the bit and the terminal on which the voltage acts and data that had been held in the bit is lost as a result.
This phenomenon is called disturbance in a nonvolatile memory. A particular type of this disturbance is drain disturbance, which occurs when a voltage acts on the drain. Because the drain side edge of the gate electrode is square, a field concentration arises at this edge, and drain disturbance is sometimes caused with this as the reason.
To avoid this, as disclosed in Japanese Patent Application Laid-Open No. H. 5-299662 and Japanese Patent Application Laid-Open No. H. 6-237004, methods for suppressing drain disturbance by rounding off the drain side edge of a floating gate constituting the charge holding part so that a field concentration does not arise there are known. In the method disclosed in Japanese Patent Application No. H. 6-237004, a first insulating film, a polysilicon layer, a second insulating film and another polysilicon layer are formed and then anisotropic dry etching is carried out vertically as far as midway through the first insulating film. The etched side wall parts are then covered with a protecting film and isotropic etching is carried out to round both of the bottom edges of the floating gate. In the method disclosed in Japanese Patent Application Laid-Open No. H. 5-299662, a first insulating film, a polysilicon layer, a second insulating film and another polysilicon layer formed successively are anisotropically dry-etched vertically to form a gate oxide film, a floating gate, another gate oxide film and a control gate are formed. Then, with a source side region masked, the gate oxide film on the drain side is isotropically etched and the floating gate edge on the drain side is thereby exposed. After that, rounding of the drain side edge of the floating gate is carried out by thermal oxidation.
However, in these methods, the process of rounding the drain side edge of the floating gate carried out to suppress drain disturbance necessitates etching steps of anisotropic dry etching and isotropic etching.
It is therefore a second object of the invention to provide a manufacturing method by which it is possible to fabricate a two-layer gate type semiconductor memory device with which drain disturbance can be suppressed without isotropically etching the gate oxide film on the drain side.
SUMMARY OF THE INVENTION
To achieve the above-mentioned first object, a semiconductor memory device provided by the present invention has formed on a semiconductor substrate a source and a drain of a second conductive type, a two-layer gate electrode, an electric-field moderating layer and a first conductive type region formed in contact with a side surface (channel region side) and a bottom surface of the electric-field moderating layer. The first conductive type region in contact with the bottom surface of the field-moderating layer is formed with a lower substantial impurity concentration than that of the first conductive type region formed at the channel region side of the field-moderating layer.
Because the substantial impurity concentration of the first conductive type region in contact with the bottom surface of the electric-field moderating layer is made lower than the impurity concentration of the first conductive type region at the channel region side of the electric-field moderating layer, it is possible to suppress narrowing of the width of a depletion layer formed between both the electric-field moderating layer and the drain and the first conductive type region in contact with the bottom surface of the field-moderating layer and thereby prevent increase of a diffusion capacitance. By this means it is possible to quicken writing speed while suppressing a delay in switching speed in the semiconductor memory device.
A semiconductor memory device according to the present invention can be manufactured by the following procedure. First, a two-layer gate electrode is formed on a semiconductor substrate and then a source and a drain are formed. Then, diagonal ion implantation of a second conductive type impurity is carried out at a first angle (&thgr;
1
) to the vertical to the semiconductor substrate surface to form an electrical-field moderating layer. Also, diagonal ion implantation of a first conductive type impurity is carried out at a second angle (&thgr;
2
) greater than the

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