Method of forming shallow trench isolation by HDPCVD oxide

Details Method of forming shallow trench isolation by HDPCVD oxide Method of forming shallow trench isolation by HDPCVD oxide

1997-02-03

2001-01-09

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C438S427000, C438S296000

Reexamination Certificate

active

06171896

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming planarized shallow trench isolation in the fabrication of integrated circuits.
(2) Description of the Prior Art
Shallow trench isolation (STI) is gaining substantial interest for deep sub-micron processes. To achieve good planarity after STI, chemical mechanical polishing (CMP) is a more promising solution than is etchback. However, due to pad deformation, the trench open area is susceptible to dishing which causes oxide thinning in the wide trench. In addition, the pattern dependency of CMP leads to non-uniform oxide removal on the silicon nitride underlayer of different dimensions. In order to remove all the oxide on the silicon nitride before nitride stripping, overpolishing is generally carried out at the cost of severe oxide dishing and silicon nitride erosion.
FIG. 1
illustrates a partially completed integrated circuit device of the prior art. A pad oxide layer
12
and a silicon nitride layer
14
have been deposited over the surface of a semiconductor substrate
10
. Trenches in the substrate have been filled with an oxide
17
which has been polished using CMP. Oxide dishing and silicon nitride erosion can both be seen in area
19
.
In order to reduce these problems, the use of a reverse tone mask at the device pattern layer has been proposed. But, due to the great difficulties in overlaying the device pattern mask and reverse-tone device pattern mask on a non-planarized oxide surface, this approach becomes very challenging for deep sub-micron processes.
U.S. Pat. No. 5,275,965 to Manning shows a method of forming trench isolation using gated sidewalls. U.S. Pat. No. 5,494,857 to Cooperman et al teaches CMP shallow trenches using a reverse-tone mask and a silicon nitride polish stop layer. U.S. Pat. No. 5,518,950 to Ibok et al shows a method in which spin-on-glass in trenches is covered with a resist mask to increase the spin-on-glass thickness over the trenches.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the invention is to provide a process for forming planarized shallow trench isolation in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming planarized shallow trench isolation in which oxide dishing is eliminated.
Still another object is to provide a process for forming planarized shallow trench isolation in which silicon nitride erosion is reduced.
Yet another object of the invention is to provide a process for forming planarized shallow trench isolation in which CMP uniformity is improved.
In accordance with the objects of the invention, a method for forming planarized shallow trench isolation is achieved. A pad oxide layer is grown over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches are etched through the nitride and pad oxide layers into the semiconductor substrate wherein there are at least one first wide nitride region between two of the trenches and at least one second narrow nitride region between another two of the trenches. A high density plasma oxide layer is deposited over the nitride layer and within the isolation trenches wherein the high density plasma oxide layer fills the isolation trenches and wherein the high density plasma oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer. A photoresist mask is formed over the high density plasma oxide layer. The substrate is exposed to actinic light wherein a central portion of the first region is exposed. The high density plasma oxide layer is etched away where it has been exposed. The high density plasma oxide layer remaining is polished away whereby the substrate is planarized and fabrication of said integrated circuit device is completed.


REFERENCES:
patent: 4916087 (1990-04-01), Tateoka et al.
patent: 5275965 (1994-01-01), Manning
patent: 5459096 (1995-10-01), Venkatesan et al.
patent: 5492858 (1996-02-01), Bose et al.
patent: 5494854 (1996-02-01), Jain
patent: 5494857 (1996-02-01), Cooperman et al.
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5518950 (1996-05-01), Ibok et al.
patent: 5531834 (1996-07-01), Ishizuka et al.
patent: 5578519 (1996-11-01), Cho
patent: 5686356 (1997-11-01), Jain et al.
patent: 5783488 (1998-07-01), Bothra et al.

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