Semiconductor device isolation structure and fabrication...

Details Semiconductor device isolation structure and fabrication... Semiconductor device isolation structure and fabrication...

1998-05-22

2001-04-10

Crane, Sara (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S423000, C438S528000, C257S506000

Reexamination Certificate

active

06214657

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device isolation structure and a semiconductor device fabrication method using the same.
2. Description of the Prior Art
A junction isolation structure is not appropriate under high voltage and high radioactive environments. This is because a high voltage supply of about 30V may lead to a junction breakdown, and a photo-electric current generated in a pn junction by gamma rays may be transient under high radioactive environments. A SOI (Silicon On Insulator) technology is a device isolation method for entirely surrounding a semiconductor device with an insulator rather than adopting a pn junction isolation structure, enabling operation notwithstanding the existence of high voltage and high radioactive environments.
In the SOI technology, fabrication steps are more simplified than fabrication steps required for a circuit formed from bulk silicon. Furthermore, using the SOI technology, a latch-up is prevented in a CMOS (Complementary Metal Oxide Semiconductor) circuit. Still further, using the SOI technology, capacitive coupling between circuits is decreased in an identical semiconductor substrate, leading to a decrease in the semiconductor chip size.
U.S. Pat. No. 5,438,015 discloses an SOI related convention art using a buried air gap, which SOI technology will be described with reference to
FIGS. 1A through 1D
.
First, as shown in
FIG. 1A
, a field oxide film
31
is formed via a general LOCOS (LOCos Oxidation of Silicon) method. In the conventional art, the field oxide film
31
is preferably from about 3000 A to 10000 A in thickness.
As further shown in
FIG. 1B
, using the field oxide film
31
on the semiconductor substrate
30
as a mask, nitride ions are implanted into the substrate
30
at a density ranging from 1×10
18
to 2×10
18
atoms/cm
2
and an energy of 100~200 KeV. The resulting structure is then annealed for about 1 to 5 hours at a temperature ranging from 1100° C. to 1300° C. to form buried silicon nitride layers
32
, whereby a plurality of active regions
33
are isolated by the buried silicon nitride layers
32
and the field oxide film
31
.
Referring to
FIG. 1C
, a plurality of holes
34
are formed adjacent to edge portions, the holes being formed sufficiently deep to reach the buried silicon nitride layers
32
. The semiconductor substrate
30
is then dipped into a hot phosphoric acid solvent, which has the characteristics of an etchant. When dipped, the solvent flows to the buried silicon nitride layers
32
through the holes
34
and etches those buried silicon nitride layers
32
to form buried gaps
35
.
With reference to
FIG. 1D
, in order to carry out an annealing process and to compensate for possible defects in the semiconductor substrate
30
, the holes
34
are filled with a silicon oxide material or a silicon nitride material via CVD (Chemical Vapor Deposition) method or a PVD (Physical Vapor Deposition) method. Reference numeral
36
denotes the silicon oxide material or the silicon nitride material which is stuffed in the holes
34
. Then, the semiconductor substrate
30
is annealed at a temperature ranging from 900~1000° C. In addition, to improve a device isolation effect, a silicon oxide film may be formed in the buried gaps prior to filling the holes
34
therewith.
When the device isolation process is completed, devices such as a gate electrode, a source and a drain are formed on the active region
33
.
However because such an SOI technique employs a LOCOS method, it has been difficult to overcome disadvantages that belong to the conventional device isolation technique employing a LOCOS method. That is, a bird's beak formation confines the decrease of the active regions, thereby deteriorating integration in the semiconductor device.
Further, because of the bird's beak phenomenon, the implanted depth becomes different depending on whether it is an edge portion or a central portion on the active region when nitride ions are implanted into the substrate for forming the buried insulator. The differentiated depths may cause a threshold voltage variation on the active region. Also, a stress-oriented defect may be encountered when the field oxide film is formed adjacent to the bird's beak in the substrate.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device isolation structure and a semiconductor device fabrication method using the same, which applies a SOI technique rather than a LOCOS method.
To achieve the above-described object, there is provided a semiconductor device isolation structure which includes a semiconductor substrate including an active region and a field region, an insulation layer buried in the active region of the substrate, and an isolation layer formed in the field region of the substrate deeper than the buried insulation layer.
Further, to achieve the above-described object, there is provided a method for isolating a semiconductor device which includes the steps of preparing a semiconductor substrate, defining an active region and a field region in the substrate, forming an insulation layer buried in the active region of the substrate, and forming an isolation layer in the field region of the substrate to be deeper than the buried insulation layer.
Still further, to achieve the above-described object, there is provided a semiconductor device according to the present invention which includes a semiconductor substrate including an active region and a field region, an insulation layer buried in the active region of the substrate, a trench isolation layer formed in the field region of the substrate to be deeper than the buried insulation layer, a gate insulation layer formed on the field region of the substrate, a gate electrode formed of a first conductive layer formed on an upper surface of the gate insulation layer, and an impurity region formed in the substrate and adjacent to each side of the gate electrode.
Also, to achieve the above-described object, the semiconductor device fabrication method according to the present invention includes the steps of sequentially stacking an oxide film and a nitride film on the substrate, defining an active region and a field region on the nitride film, forming a silicon nitride film pattern over the field region of the substrate, forming an insulation layer buried in the active region of the substrate, forming a gate insulation layer on the active region of the substrate, forming a first conductive layer on the gate insulation layer, forming a first insulation layer on the first conductive layer, forming a first conductive layer pattern by exposing the nitride film pattern and the first conductive layer therethrough, forming an oxide film by oxidizing the first conductive pattern, forming a trench in the field region of the substrate to be deeper the buried insulation layer, forming a second insulation layer on the trench and the oxide film, exposing the first conductive layer pattern, forming a second conductive layer on the first conductive layer, forming a word line by patterning the second conductive layer, forming a gate electrode by patterning the first conductive layer below the second conductive layer, and forming an impurity region in the semiconductor substrate and adjacent to each side of the gate electrode.


REFERENCES:
patent: 5438015 (1995-08-01), Lur
patent: 5494846 (1996-02-01), Yamazaki
patent: 5627399 (1997-05-01), Fujii
patent: 5696020 (1997-12-01), Ryum et al.
patent: 5956597 (1999-09-01), Furukawa et al.
patent: 6057214 (2000-05-01), Joyner

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