Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-06
2001-10-02
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S411000, C438S591000, C438S785000
Reexamination Certificate
active
06297539
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit (IC) fabrication processes and, more particularly, to a high dielectric constant gate insulation film, and a deposition method for such film.
Current Si VLSI technology uses SiO
2
, or nitrogen containing SiO
2
, as the gate dielectric in MOS devices. As device dimensions continue to scale down, the thickness of the SiO
2
layer must also decrease to maintain the same capacitance between the gate and channel regions. Thicknesses of less than 2 nanometers (nm) are expected in the future. However, the occurrence of high tunneling current through such thin layers of SiO
2
requires that alternate materials be considered. Materials with high dielectric constants would permit gate dielectric layers to be made thicker, and so alleviate the tunneling current problem. These so-called high-k dielectric films are defined herein as having a high dielectric constant relative to silicon dioxide. Typically, silicon dioxide has a dielectric constant of approximately 4, while high-k films have a dielectric constant of greater than approximately 10. Current high-k candidate materials include titanium oxide (TiO
2
), zirconium oxide (ZrO
2
), tantalum oxide (Ta
2
O
5
), and barium and strontium titanium oxide (Ba,Sr)TiO
3
. One common problem associated with the above-mentioned high-k dielectrics is that they develop a crystalline structure under
normal preparation conditions. As a result, the surface of the film is very rough. Surface roughness causes non-uniform electrical fields in the channel region adjacent the dielectric film. Such films are not suitable for the gate dielectrics of MOSFET devices.
Because of high direct tunneling currents, SiO
2
films thinner than 1.5 nm cannot be used as the gate dielectric in CMOS devices. There are currently intense efforts in the search for the replacement of SiO
2
, with TiO
2
and Ta
2
O
5
attracting the greatest attention. However, high temperature post deposition annealing, and the formation of an interfacial SiO
2
layer, make achieving equivalent SiO
2
thicknesses (EOT) of less than 1.5 nm very difficult.
It would be advantageous if a high-k dielectric film could be used as an insulating barrier between a gate electrode and the underlying channel region in a MOS transistor.
It would be advantageous if improved high-k dielectric materials could be formed by simply doping, or otherwise adding additional elements to currently existing high-k dielectric materials.
It would be advantageous if the electrical properties, including electron affinity, of the high-k dielectric materials could be modified by simply doping, or otherwise adding additional elements to currently existing high-k dielectric materials.
SUMMARY OF THE INVENTION
Accordingly, a thin film having a high dielectric constant (10 to 25) is provided. The film including a doping metal, a metal selected from the group consisting of zirconium (Zr) and hafnium (Hf), and oxygen. The doping metal is preferably a trivalent metal, such as aluminum (Al), scandium (Sc), lanthanum (La), or yttrium (Y), or a divalent metal, such as calcium (Ca) or strontium (Sr).
By selecting the doping metal, it is possible to vary the electron affinity of the dielectric material deposited. By varying the electron affinity it is possible to vary the electron barrier height and the hole barrier height. Accordingly, the present invention allows one to modify the electron affinity of the dielectric film while producing a film with a higher dielectric constant than silicon dioxide. In addition, the presence of the doping metal tends to produce amorphous dielectric materials since the presence of the doping metals reduces, or eliminates, the formation of crystalline structures.
The present invention provides, in part, zirconia (ZrO
2
) stabilized by Y
2
O
3
, CaO
2
, Al
2
O
3
, La
2
O
3
, La and Sr. In another embodiment SrZO
3
is provided as a dielectric material.
Typically, the percentage of doping metal in the film does not exceed approximately 50%. In some applications the percentage of doping metal will be less than approximately 10%, in which case the film produced may not be amorphous.
Also provided is a MOSFET transistor. The transistor comprising a gate electrode, a channel region having a top surface underlying said gate electrode, and a gate dielectric film interposed between the gate electrode and the channel region top surface. The content of the dielectric film is as described above. Typically, the gate dielectric film has a thickness in the range of approximately 20 and 200 Å.
Some aspects of the invention further comprise the transistor having an interface barrier, with a thickness in the range of approximately 2 to 5 Å, interposed between the channel region and the gate dielectric film. The interface materials are selected from the group consisting of silicon nitride and silicon oxynitride, whereby the channel region top surface is made smoother to prevent the degradation of electron mobility of the MOSFET.
In the fabrication of an integrated circuit (IC) having a surface, a sputtering method is also provided to form a doped metal oxide film on the IC surface. The method comprises the steps of:
a) establishing an atmosphere including oxygen;
b) sputtering at least one target metal including a metal selected from the group consisting of Zr and Hf, and a doping metal, such as Ca, Sr, Al, Sc, La, or Y, on the IC silicon surface;
c) in response to Steps a) and b), forming the doped metal oxide film; and
d) annealing at a temperature in the range of approximately 400 and 900 degrees C., whereby a thin film having a high dielectric constant and good insulating properties is formed.
In some aspects of the invention Step a) includes co-sputtering with separate targets including a first target of a metal selected from the group consisting of Zr and Hf, and a second target of the doping metal in an oxidizing atmosphere.
Alternately, a chemical vapor deposition (CVD) method of depositing the doped metal oxide film is provided comprising the steps of:
a) preparing at least one precursor, including a metal selected from the group consisting of Zr and Hf, and a doping metal;
b) vaporizing the precursor;
c) establishing an atmosphere including oxygen;
d) decomposing the precursor on the IC surface to deposit, by chemical vapor deposition (CVD), an alloy film including the metal selected from the group consisting of Zr and Hf, the doping metal, and oxygen; and
e) annealing at a temperature in the range of approximately 400 to 900 degrees C., whereby a thin film having a high dielectric constant and good barrier properties is formed.
In another alternative embodiment, atomic layer chemical vapor deposition (ALCVD), which is also known as atomic layer deposition (ALD), is employed as a method of depositing the doped metal oxide film. The ALCVD method comprises the steps of:
a) preparing a first precursor including a metal selected from the group consisting of Zr and Hf;
b) vaporizing the first precursor and exposing the IC surface to the precursor, whereby a layer, preferably a monolayer, of the metal is chemically adsorbed to the surface to deposit, by ALCVD, the layer of metal;
c) preparing an oxygen precursor;
d) vaporizing the oxygen precursor and exposing the IC surface to the oxygen precursor, whereby a layer, preferably a monolayer, of oxygen is chemically adsorbed to the surface to deposit, by ALCVD, the layer of oxygen;
e) preparing a doping metal precursor, which includes a doping metal;
f) vaporizing the doping metal precursor and exposing the IC surface to the doping metal precursor, whereby a layer of the doping metal is chemically adsorbed to the surface to deposit, by ALCVD, the layer of doping metal; and
g) annealing at a temperature in the range of approximately 300 to 900 degrees C. to condition the deposited layers, whereby a thin film having a high dielectric constant and good barrier properties is formed.
By repeating the steps as necessary, multiple layers of each material in the dielectric may
Ma Yanjun
Ono Yoshi
Clark Sheila V.
Krieger Scott C.
Rabdau Matthew D.
Ripma David C.
Sharp Laboratories of America Inc.
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