Method of manufacturing an insulated trench gate...

Details Method of manufacturing an insulated trench gate... Method of manufacturing an insulated trench gate...

2000-01-18

2001-04-24

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06221721

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and particularly to a device structure with a low on-state voltage for an insulated gate bipolar transistor having trench MOS gate and a method of manufacturing the same.
2. Description of the Background Art
FIG. 47
is a sectional view of a conventional insulated gate semiconductor device. An insulated gate bipolar transistor (referred to as an IGBT, hereinafter) with trench gate structure (an IGBT with the trench gate structure is referred to as a U-type IGBT) will be described herein by way of example.
Recently, IGBTs are used in voltage resonance circuits, which are high-frequency inverters for achieving energy saving and reduction in size and weight of household electric appliances, in intelligent power modules for performing variable speed control of three-phase motors in the fields of general-purpose inverters, AC servos, air conditioners, and the like, and the use thereof are becoming common. While the switching characteristics, the saturation voltage, and the SOA (Safe Operating Area) are in the trade-off relation in the IGBTs, which are key devices thereof, devices with good switching characteristics, low saturation voltage and large SOA are required.
In
FIG. 47
, reference character
1
denotes a P
+
collector layer,
2
denotes an N
−
layer,
3
denotes a P base layer,
4
denotes an N
+
emitter region,
5
denotes a trench,
6
denotes a gate insulating film,
7
denotes a gate electrode,
8
denotes an interlayer insulating film,
9
denotes an N
+
buffer layer,
10
denotes an emitter electrode,
11
denotes a collector electrode and
12
denotes a channel region.
Next, operation of the IGBT will be described. When a certain collector voltage V
CE
is applied between the emitter electrode
10
and the collector electrode
11
and a certain gate voltage V
GE
is applied between the emitter electrode
10
and the gate electrode
7
, that is, when the gate is turned on, the channel region
12
is inverted to N type and a channel is formed. Then electrons are injected into the N
−
layer
2
through this channel from the emitter electrode
10
.
These injected electrons forwardly biases the P
+
collector layer
1
and the N
−
layer
2
and holes are injected from the collector electrode
11
through the P
+
collector layer
1
and the N
+
buffer layer
9
into the N
−
layer
2
. As a result, the resistance of the N
−
layer
2
considerably decreases due to conductivity modulation and the current capacity of the IGBT increases. The voltage drop between collector and emitter of the IGBT at this time is an on-state voltage (V
CE(SAT)
).
Next, to turn the IGBT from the on state to the off state, the gate voltage V
GE
applied between the emitter electrode
10
and the gate electrode
7
is brought to 0V or reverse bias, that is, the gate is turned off, then the channel region
12
inverted into the N type returns to the P type and injection of electrons from the emitter electrode
10
stops. Subsequently the electrons and holes accumulated in the N
−
layer
2
go through to the collector electrode
11
and the emitter electrode
10
, respectively, or they are recombined and disappear.
Generally, the on-state voltages of the IGBTs are mostly determined by substantial resistance of the N
−
layer
2
necessary to keep the breakdown voltage. Factors for the substantial resistance include the electron supplying capability of MOSFET forming the IGBT. The structure of the U-type IGBT in which a narrow and deep trench is formed in the chip surface and an MOSFET is formed on its side wall makes the unit cell interval as small as possible to increase the electron supplying capability of the MOSFET.
FIG. 48
is a circuit diagram showing an equivalent circuit of the IGBT. In
FIG. 48
, reference character
15
denotes a bipolar transistor and
16
denotes an MOSFET. Generally, the IGBT is represented by the equivalent circuit of FIG.
48
. However, since h
fe
of the bipolar transistor
15
formed of the P
+
collector layer
1
, the N layer including the N
+
buffer layer
9
and the N
−
layer
2
and the P base layer of the IGBT is small, the IGBT can be regarded as a combination of the MOSFET and a diode
17
.
FIG. 49
is a circuit diagram showing an equivalent circuit of the IGBT when the h
fe
of the bipolar transistor
15
is considered to be small. In
FIG. 49
, reference character
17
denotes a diode and
18
denotes an MOSFET.
FIG. 50
is a graph showing carrier concentration distribution of the N
−
layer of a PIN diode in an on state.
In
FIG. 49
, since the MOSFET
18
can be regarded as a mere switching element, the N
−
layer of the PIN diode
17
of the IGBT should have such carrier concentration distribution of the N
−
layer of the PIN diode as shown in
FIG. 50
, but it does not.
FIG. 51
is a graph showing the carrier concentration distribution of the N
−
layer
2
of the conventional IGBT in an on state. While the carrier concentration of the N
−
layer of the PIN diode in an on state is uniform between the end on the anode side of the N
−
layer and the end on the cathode side as shown in
FIG. 50
, the carrier concentration of the N
−
layer
2
in an on state of the conventional IGBT gradually decreases from the end on the collector side of the N
−
layer
2
toward the end on the emitter side, as shown in FIG.
51
. Accordingly, the on-state voltage of the conventional IGBT is higher than that of the diode.
Especially, in IGBTs with high breakdown voltage, the breakdown voltage is ensured by increasing the thickness of the N
−
layer
2
. The gradient of the carrier concentration of the N
−
layer
2
decreasing from the collector side end to the emitter side end is not affected by the thickness of the N
−
layer
2
if the carrier life time is the same, so that the difference in height of the carrier concentration between the collector side end and the emitter side end increases as the thickness of the N
−
layer
2
becomes larger, therefore the difference in on-state voltage from the diode becomes larger as the IGBT has a higher breakdown voltage.
Various devices are proposed to eliminate such difference between the on-state voltage of the IGBT and the on-state voltage of the diode which is regarded as an extreme value of the on-state voltage of the IGBT. Such devices include the MCT (MOS CONTROLLED THYRISTOR), and the IEGT (INJECTION ENHANCED GATE BIPOLAR TRANSISTOR).
FIG. 52
is a sectional view showing the structure of the MCT. In
FIG. 52
, reference character
21
denotes an N
+
cathode region,
22
denotes an N region,
23
denotes a P
+
region,
24
denotes a channel region for gate-on and
25
denotes a channel region for gate-off, i.e., an off-channel region. Other reference characters denote the same parts as those in FIG.
47
. It is known that the N
−
layer
2
in the MCT generally has the carrier concentration distribution in an on state similar to that of the diode. Hence, the MCT has its on-state voltage lower than that of the IGBT of the conventional structure.
At the time of turning off, however the P-channel MOS formed of the P base layer
3
, the N region
22
and the P
+
region
23
forms a channel by inversion of the off-channel region
25
, through which channel holes flow. Therefore, considering that the resistance of the off-channel region
25
is generally high, this produces the problem that the current value capable of off can not be taken large. Furthermore, an N-channel MOS for ON and a P-channel MOS for OFF must be formed in the threefold diffusion, which results in complicated process leading to a higher price of the device.
Examples of IEGTs include that disclosed in Japanese Patent laying-Open No.5-243561. For example, the IEGT shown in FIG. 101 of Japanese Pate

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