Semiconductor memory device connected to memory controller...

Details Semiconductor memory device connected to memory controller... Semiconductor memory device connected to memory controller...

1998-12-18

2001-10-16

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189120, C365S200000

Reexamination Certificate

active

06304502

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a memory system employing the same, and more particularly to a semiconductor memory device connected to a memory controller and a memory system employing the same.
2. Description of the Background Art
Conventionally, a memory system employing a Synclink Dynamic Random Access Memory (hereinafter referred to as an SLDRAM) has been developed. This memory system, having a plurality of SLDRAMs connected in parallel corresponding to a memory controller, sequentially transfers data in synchronization with a clock signal. Therefore a high speed data transfer is allowed.
Japanese Patent Laying-Open No. 9-293393 discloses a technique for repairing (utilizing without discarding) a memory system when a defective SLDRAM is found after memory system completion. According to this technique, a built in test circuit, provided with each SLDRAM, tests a corresponding SLDRAM at system initialization to determine whether the SLDRAM is normal or not and transfers a test result to the memory controller. Hence, an ID value is not given to a defective SLDRAM and the memory controller is prevented from accessing to a defective SLDRAM, whereby system malfunction is prevented.
In a conventional technique, however, memory system performance is significantly deteriorated by an existence of even a single defective bit in an SLDRAM. An access to an SLDRAM is inhibited if one defective bit exists in the SLDRAM, that is, one defective bit in an SLDRAM means a loss of entire memory capacity of the SLDRAM from the memory system capacity.
SUMMARY OF THE INVENTION
A main object of the present invention is to provide a semiconductor memory device and a memory system allowing an efficient system utilization (repair) even when a defective address is found after the memory system completion and being capable of suppressing memory capacity decrease.
According to one aspect of a semiconductor memory device of the present invention, a first memory circuit tests each memory cell in the memory circuit to determine whether it is normal or not in response to a first test execution command and provides a test result information including an address of a defective memory cell to a memory controller. Therefore the memory controller can access only to a normal memory cell other than a defective memory cell even when a defect is developed in a memory cell after system completion. Therefore the rate of memory capacity decrease of the memory system can be suppressed compared with a conventional technique where an access is inhibited to a semiconductor memory device having a memory cell which becomes defective after memory system completion.
Preferably, the test result information further includes the number of defective memory cells. In this case, as the memory controller can confirm the number of defective memory cells, the test result information can be processed correctly and quickly.
According to another aspect of a semiconductor memory device of the present invention, a first memory circuit tests each memory cell in each memory circuit to determine whether it is normal or not in response to a first test execution command and provides a test result information including an address of a defective memory circuit having a defective memory cell to a memory controller. Therefore the memory controller can access only to a normal memory circuit other than a defective memory circuit even when a memory circuit is made defective after system completion. Therefore the rate of memory capacity decrease of the memory system can be suppressed compared with a conventional technique where an access is inhibited to a semiconductor memory device having a memory cell made defective after memory system completion.
Preferably, the test result information further includes the number of defective memory circuits. In this case, the memory controller can confirm the number of defective memory circuits, whereby correct and rapid processing of the test result information is allowed.
Preferably, the first test circuit temporarily stores the test result information and supplies it to the memory controller in response to a test result output command sent from the memory controller. When a plurality of a semiconductor memory devices are connected to the memory controller, the plurality of semiconductor memory devices can be tested at the same time and a test result of each semiconductor memory device can be sequentially transferred to the memory controller, whereby test time can be shortened.
Preferably, the semiconductor memory device further includes a logic circuit processing data between the memory controller and the memory circuit and a second test circuit testing the logic circuit to determine whether it is normal or not in response to a second test execution command sent from the memory controller and providing a test result to the memory controller, and the memory circuit and the logic circuit are separately usable from the memory controller side. Hence, when only the logic circuit is defective, the semiconductor memory device can be used as a memory circuit and when only the memory circuit is defective, the semiconductor memory device can be used as a logic circuit.
In a memory system of the present invention, the first test circuit of a semiconductor memory device tests each memory cell in the memory circuit to determine whether it is normal or not in response to the first test execution command and supplies the test result information including an address of a defective memory cell to the memory controller, which accesses only a normal memory cell based on the test result information. Therefore the rate of memory capacity decrease of the memory system can be suppressed compared with a conventional technique where an access is inhibited to a semiconductor memory device having a memory cell made defective after memory system completion.
Preferably, the test result information further includes the number of defective memory cells. In this case, as the memory controller can confirm the number of defective memory cells, the test result information can be processed correctly and quickly.
Preferably, the memory controller includes a register for storing the test result information provided from the first test circuit, and an address generation circuit generating only an address corresponding to a normal memory cell in the memory circuit based on an externally supplied external address and the test result information stored in the register, and providing the address to a read/write circuit. Thus the memory controller can be easily configured.
Preferably, the first test circuit temporarily stores the test result information and supplies it to the memory controller in response to a test result output command sent from the memory controller. When a plurality of a semiconductor memory devices are connected to the memory controller, the plurality of semiconductor memory devices can be tested at the same time and a test result of each semiconductor memory device can be sequentially transferred to the memory controller, whereby test time can be shortened.
Preferably, the semiconductor memory device further includes a logic circuit processing data between the memory controller and the memory circuit and a second test circuit testing the logic circuit to determine whether it is normal or not in response to a second test execution command sent from the memory controller and providing a test result to the memory controller, and the memory circuit and the logic circuit are separately usable from the memory controller side. Hence, when only the logic circuit is defective, the semiconductor memory device can be used as a memory circuit and when only the memory circuit is defective, the semiconductor memory device can be used as a logic circuit.
Still preferably, there is a plurality of semiconductor memory devices, each being allocated a unique identifier, and each semiconductor memory device is activated in response to a corresponding identifier sen

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