Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-14
2001-08-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S246000, C438S249000, C438S386000, C438S387000, C438S389000, C438S392000, C438S433000, C438S434000, C438S436000, C438S437000, C438S438000
Reexamination Certificate
active
06281068
ABSTRACT:
FIELD OF INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits (Ics) and more particularly to an improved method for forming the buried plate regions in deep trench capacitors of DRAM memory chips.
BACKGROUND OF THE INVENTION
Deep trenches are extensively used in the manufacture of semiconductor integrated circuits, in particular of 64 and 256 Mb DRAM memory chips to define the storage capacitors. Basically, a deep trench is formed in a doped silicon substrate, then a dielectric film is conformally deposited thereon to coat the entire interior surface of the trench and finally the trench is filled with doped polysilicon. This doped silicon/dielectric film/doped polysilicon forms the storage capacitor. In order to keep an acceptable capacitor value in spite of continuous capacitor size reduction, the thickness of the capacitor dielectric film is constantly reduced. In turn, the voltage across dielectric film must be drastically reduced to avoid undesired breakdown voltage effects. In order to achieve this voltage reduction, a doped area is created around the bottom of the storage capacitor. This area is commonly referred to as the “buried plate” in the technical literature. At this stage of a conventional fabrication process of such DRAM chips, the starting structure (which is a part of a wafer) consists of a silicon substrate coated with silicon oxide and silicon nitride pad layers having deep trenches formed therein. Difficulties have been experienced in forming the buried plate in the deep trenches.
SUMMARY OF THE PRESENT INVENTION
It is therefore a primary object of the present invention to provide an improved method for buried plate formation in deep trench capacitors.
It is another object of the present invention to provide an improved method for buried plate formation in deep trench capacitors that uses a polymer having high filling/planarizing capability and is RIE etchable instead of the standard photoresist material.
It is another object of the present invention to provide an improved method for buried plate formation in deep trench capacitors that allows a very accurate control of the polymer etch back step which is essential to the whole chip fabrication process.
It is another object of the present invention to provide an improved method for buried plate formation in deep trench capacitors which does not require the use of a CDE tool to perform the standard photoresist etch back step.
It is another object of the present invention to provide an improved method for buried plate formation in deep trench capacitors wherein the polymer is RIE etched back for greater etch uniformity, wafer to wafer and lot to lot.
It is still another further object of the present invention to provide an improved method for buried plate formation in deep trench capacitors wherein the polymer etch back step is monitored by optical/interferometric techniques.
The accomplishment of these and other related objects is achieved by the method of the present invention which aims to get rid of the drawbacks of the prior art buried plate formation process. According to the present invention, there is disclosed an improved method that is based on the combined use of a new filling/planarizing medium and a new etch back process.
The starting structure is state-of-the-art and consists of a silicon substrate coated by a patterned SiO
2
SiN
4
pad layer to define deep trenches formed therein by etching. The interior walls of said deep trenches are coated with an arsenic-doped silicon glass (ASG) layer and an overlying SiO
2
passivation layer that are conformally deposited onto the structure as standard.
Now, at this stage of the conventional buried plate formation process, a polymer having high filling/planarization capability on the one hand and being RIE etchable on the other hand, such as the polymer references ACCUFLO T-13EL, manufactured by ALLIEDSIGNAL, Inc., Sunnyvale, Calif., USA, is used to replace the photoresist material. This polymer is deposited to fill the deep trenches in excess and then baked to leave a layer having a very planar surface above the silicon substrate.
The polymer is then etched in a RIE tool using an O
2
/CF
4
chemistry. Because now an optical/interferometric etch end point detection system can be used to monitor the etch back step in its totality, the quantity of the polymer remaining in deep trenches can be thus very accurately controlled, which in turn will produce a well controlled buried plate region during the out diffusion step of the arsenic dopant contained in the ASG layer.
The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as these and other objects and advantages thereof, will be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5336912 (1994-08-01), Ohtsuki
patent: 5618751 (1997-04-01), Golden et al.
patent: 5629226 (1997-05-01), Ohtsuki
patent: 6001684 (1999-12-01), Shen
patent: 6008103 (1999-12-01), Hoepfner
patent: 6100130 (2000-08-01), Iba et al.
patent: 6107135 (2000-08-01), Kleinhenz et al.
Coronel Philippe
Cruau David
Leverd Francois
MacCagnan Renzo
Mass Eric
Gurley Lynne A.
International Business Machines - Corporation
Niebling John F.
Walsh Robert A.
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