Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-19
2001-09-04
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S272000, C257S331000
Reexamination Certificate
active
06284604
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a field-effect-controllable, vertical semiconductor component, including a semiconductor body, at least one drain zone of a first conduction type, at least one source zone of the first conduction type, at least one gate electrode insulated from the entire semiconductor body by a gate oxide, and a bulk region of the first conduction type. The invention also relates to a method for producing a field-effect-controllable, vertical semiconductor component.
Field-effect-controllable semiconductor components of that kind are, for example, MOS field-effect transistors (MOSFETs) Such MOSFETs have been known for a long time and are described, for example, in the Siemens-Datenbuch [Data Manual] 1993/94 SIPMOS-Halbleiter, Leistungstransistoren und Dioden [SIPMOS Semiconductors, Power Transistors and Diodes], pp. 29 ff. FIG. 4 on page 30 of that data manual shows the basic layout of a power transistor of that kind. The transistor shown there is a vertical n-channel SIPMOS transistor. In such a transistor, the n
+
substrate serves as a carrier with the drain metallizing beneath it. Above the n
+
substrate, an n-epitaxial layer follows, which is variously thick and correspondingly doped depending on the depletion voltage. The gate over that, made of n
+
polysilicon, is embedded in insulating silicon dioxide and acts as an implantation mask for the p well and the n
+
source zone. The source metallizing covers the entire structure and connects the individual transistor cells of the chip in parallel. Further details of that vertically constructed power transistor can be found on pages 30 ff. of the aforementioned data manual.
A disadvantage of such a configuration is that the on-state resistance R
on
of the drain-to-source load path increases with increasing dielectric strength of the semiconductor component, since the thickness of the epitaxial layer necessarily increases. At 50V, the on-state resistance R
on
per unit of surface area is approximately 0.20 &OHgr;mm
2
, and rises at a depletion voltage of 1000V to a value of approximately
10 &OHgr;mm
2
,for instance.
In contrast to lateral MOSFETs, vertical MOSFETs have a substantially vertical current flow direction. That causes the current to flow from the front side of the wafer to the rear side of the wafer. In vertical MOSFETs of that generic type, the source and gate terminals are located on the front side of the wafer, while the drain terminal is contacted through the rear side of the wafer. As a result, vertical MOSFETs have the advantage over lateral MOSFETs of being integratable on the semiconductor chip in a space-saving way, and therefore the components can be manufactured less expensively.
Vertical MOSFETs are typically secured by the rear side of the wafer to a cooling body or to the device housing. One disadvantage of such a configuration is that an insulating layer must be applied between the drain rear side contact and the cooling body, which typically is at the potential of the device ground. The insulating layer increases the heat resistance between the drain rear side contact and the cooling body. That leads to reduced heat dissipation through the rear side of the wafer.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a field-effect controllable, vertical semiconductor component and a method for producing the same, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a field-effect-controllable, vertical semiconductor component, comprising a semiconductor body having front and rear wafer sides; at least one drain zone of a first conduction type; at least one source zone of the first conduction type; at least one gate electrode; a gate oxide insulating the at least one gate electrode from the entire semiconductor body; and a bulk region of the first conduction type; a source terminal disposed on the rear wafer side; and a drain terminal and a gate terminal disposed on the front wafer side.
In accordance with another feature of the invention, the source terminal is secured to a cooling body, in particular a copper block. This makes the heat resistance between the source contact and the cooling body less by approximately a factor of 5. Improved heat dissipation through the rear side of the wafer is thereby made possible in particular because of the very good thermal conductivity of copper. This allows even further miniaturization of the components according to the invention.
In accordance with a further feature of the invention, other embodiments of the vertical MOSFETs are provided. Vertical trenches are provided that are filled with conductive material. Titanium nitride, highly doped polysilicon, metal silicide, or metal is preferably used as the conductive material, all because of their good conductivity. The trenches short-circuit the source zones on the front side of the wafer with the bulk region on the rear side of the wafer. The current is therefore conducted at low impedance from the front side of the wafer to the source terminal on the rear side of the wafer. An important feature in this case is that the bulk region is doped highly enough to assure a low-impedance connection between the front side of the wafer and the rear side of the wafer.
In accordance with an added feature of the invention, there are provided vertical intercell zones, in which gate electrodes and the gate oxide are located. The gate electrode is shifted into the semiconductor body, and as a result MOSFETs with high breakdown voltages and at the same time a low turn-on resistance R
on
can advantageously be realized.
In accordance with an additional feature of the invention, there are provided ion-implanted, highly doped channel zones under the intercell zones. The turn-on voltage of the channel of the MOSFET can be adjusted in a targeted way through the use of this so-called channel implantation.
In accordance with yet another feature of the invention, there are provided contact regions in the drain zones. The contact regions for the drain terminals must have an adequately high dopant concentration to assure an ohmic contact between the semiconductor and the metallizing. An exactly determinable doping dose can be introduced and thus the desired dopant concentration can be adjusted within the desired ranges through the use of ion implantation.
In accordance with yet a further feature of the invention, polysilicon is used as gate material of the gate electrode, because from a process technology standpoint it is easy to handle and it has good conductivity.
With the objects of the invention in view, there is also provided a method for producing a field-effect-controllable, vertical semiconductor component, which comprises the following steps: depositing various epitaxial layers of an inner zone on a bulk region of a semiconductor body; epitaxially depositing drain and source zones on the inner zone; structuring a front wafer side, and introducing contact regions and highly doped source regions by ion implantation; structuring the front wafer side again, and anisotropically etching intercell zones; introducing channel zones by ion implantation using an etching mask; thermally applying a thin silicon dioxide layer as a gate oxide to trench walls of the intercell zones using the etching mask, filling the intercell zones with polysilicon as a gate material, etching excess polysilicon out of the intercell zones, and filling the intercell zones with silicon dioxide as a gate material; structuring the front wafer side once again, and anisotropically etching trenches down to a depth of the bulk zone in the region of the source zones; applying a thin oxide to walls of the trenches, and filling the trenches with conductive material; metallizing a source terminal over a large surface area on a rear wafer side; metallizing a drain terminal and a g
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
LandOfFree
Method for producing a field-effect-controllable, vertical... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing a field-effect-controllable, vertical..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing a field-effect-controllable, vertical... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2549681