Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-03
2001-07-17
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S258000, C438S267000
Reexamination Certificate
active
06261907
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device and, in particular, to a source-side-injection Electrically Erasable Programmable Read Only Memory (EEPROM) device based on a Flash cell which employs a sidewall polysilicon spacer as an Erase Gate (EG).
2. Discussion of the Prior Art
In order to realize a Flash EEPROM array having a density of 16 Mbits or higher, technology innovations in both memory cell structure and array architecture are required. In the past, Intel's well-know “T-shaped” ETOX cell has been intensively utilized in Flash memory applications because of its small cell size and simple stack gate structure. Examples of such devices are described by Jinbo et al., “A 5V-Only 16 Mb Flash Memory with Sector Erase Mode”, IEEE JSSC, P. 1547, 1992 and by Atsumi et al., “A 16 Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation”, IEEE JSSC, P. 461, 1994. However, the conventional operation issues, such as high programming current and high erase band-to-band tunneling current place severe limitations on the power supply (V
cc
) scalability and cell size scalability. In fact, band-to-band tunneling current limits V
cc
scaling in an ETOX memory array with a large sector size (i.e. 512K bits per sector) architecture. Furthermore, band-to-band tunneling current limits cell size scaling because a source junction as deep as 0.2 um is required for a 0.35 um technology. That means source lateral diffusion takes more than one third of the transistor channel length and cell scalability is severely limited.
Source side injection Flash memory cells using a polysilicon sidewall spacer as a select gate are introduced to address the high programming current issue associated with the ETOX cell. Examples of such devices are described by Wu et al., “Electrically Programmable Memory Device Employing Source Side Injection”, U.S. Pat. No. 4,794,565, 1988 and by Naruke et al., “A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side”, IEEE IEDM, P. 603, 1989. However, an individual polysilicon-sidewall-spacer line has to be strapped with a metal line in order to be switched as a word line during a read cycle and thus, memory array layout becomes metal pitch limited. Furthermore, the issue of high band-to-band tunneling current during erase was not addressed.
Jeng et al., “Single Transistor Non-volatile Electrically Alterable Semiconductor Memory Device with a Re-crystallized Floating Gate”, U.S. Pat. No. 5,067,108, 1991, proposed a source-side-injection Flash cell with a non-self-aligned select transistor. This cell is erased by a poly-to-poly tunneling mechanism and thus, band-to-band tunneling current is eliminated. With this approach, an independent select transistor with a silicide gate is used to replace the sidewall spacer select transistor and thus, metal strapping is not necessary. However, this cell has two transistors in series plus a source coupling region and thus, cell size is inherently large. Furthermore, the select gate channel length is alignment sensitive and the source junction has to sustain a high voltage, both of which undesirably limit further cell scaling.
Yuan et al. disclosed two U.S. Pat. Nos. 5,712,179 and 5,534,456 describing new EEPROM devices based on a split gate flash cell in a contactless virtual ground array. By eliminating metal contacts within memory cells, a compact flash memory array can be achieved. However, continuous source/drain bit lines introduce high bit line diffusion capacitance as well as high bit-line/word-line overlap capacitance and thus, slow down the memory access speed. Furthermore, the high programming current (>300 uA/cell) associated with the ETOX-type programming mechanism, limits cell's Vcc scalability. Consequently, although Yuan's memory arrays are suitable for low speed, high density applications such as compact flash cards, they are not designed for the high speed, low Vcc, low power applications targeted in the present invention.
SUMMARY OF THE INVENTION
It is therefore the object of this invention to provide a memory device based on a compact Flash cell and memory array requiring low currents for both program and erase operations, and thus, the device is suitable for low V
cc
, low power, high density Flash memory applications.
The inventive cell has a control gate overlapping a sized-up floating gate (by “sized-up”, it is meant that the length of the floating gate is longer than the length of the control gate) to form a stack gate. The stack gate is side by side with a sidewall spacer erase gate with a thin poly tunnel oxide between the erase gate and the floating gate, with a thicker dielectric layer between the erase gate and the control gate. The preferred cell is built on a P-type semiconductor substrate with self-aligned N-type source and drain regions. This cell is programmed by channel hot electron injection at the source side of the floating gate transistor and erased by poly-to-poly tunneling through the poly tunnel oxide. Since the poly tunnel oxide thickness is minimized, a high lateral field (at the injection point) and a fast programming speed can be obtained. In addition, cell programming current is limited to less than 1 uA which enables the memory array based on this cell to be programmed in a page mode. Therefore, high speed programming with low power consumption can be achieved. By using a poly-to-poly erase scheme, band-to-band tunneling current during erase is advantageously eliminated. Therefore, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V
cc
scaling becomes possible. Since both program and erase power consumption are low, the inventive cell is suitable for low V
cc
, low power applications.
Based on the inventive cell, a NOR-type Flash EEPROM array is organized with bit lines running in the vertical direction while control gate word lines, source lines and erase gate lines run in the horizontal direction. This array is divided into sectors in which cell data can be altered by sector erase followed by page write.
This array is fabricated with a triple polysilicon process in which the sized-up floating gate poly is defined by the control gate sidewall dielectric spacer in a self-aligned etch process. After stack gate formation, a poly tunnel oxide is grown before forming the poly sidewall spacer erase gate. Since a deep N-well and a deep source junction are not used, the process complexity is comparable to that of the ETOX architecture. By reducing the depth of the source junction, this cell size is comparable to the ETOX cell.
In another embodiment of the invention, bit line parasitic capacitance in high speed applications is addressed. Namely, since the erase gate is conductive during a normal read operation, the erase gate channel introduces an additional gate capacitance component to the bit line capacitance. In order to minimize the bit line capacitance, an alternative cell design with the sidewall spacer erase gate on the source side of the stack gate is introduced for high speed applications.
REFERENCES:
patent: 5438542 (1995-08-01), Atsumi et al.
patent: 5455792 (1995-10-01), Yi
patent: 5686332 (1997-11-01), Hong
patent: 5712179 (1998-01-01), Yuan
patent: 5838039 (1998-11-01), Sato et al.
patent: 6043530 (2000-03-01), Chang
patent: 6101131 (2000-08-01), Chang
patent: 6125060 (2000-09-01), Chang
Bowers Charles
Chen Jack
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