Methods of forming integrated circuit contact holes using...

Details Methods of forming integrated circuit contact holes using... Methods of forming integrated circuit contact holes using...

1998-11-02

2001-05-22

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S612000, C438S613000

Reexamination Certificate

active

06235623

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit fabrication methods, and more particularly to methods of forming integrated circuit contact holes.
BACKGROUND OF THE INVENTION
As the integration density of integrated circuit devices continues to increase, it may become more difficult to form contact holes for these highly integrated devices. As is well known to those having skill in the art, contact holes are used to connect conductive layers of an integrated circuit to one another, through intervening dielectric layers.
For example, as the integration density of integrated circuits continues to increase, and device patterns become smaller, exposure technology has moved to shorter wavelengths, from g-line (436 nm) to i-line (365 nm) to KrF excimer laser (248 nm) and ArF excimer laser (193 nm). However, even with the increasingly short wavelengths, it may be increasingly difficult to form patterns of 0.1 &mgr;m or less.
Multilevel resist processes have also been used to form contact holes for highly integrated devices. Unfortunately, multilevel resist processes can still produce undesired short circuits between adjacent contacts.
FIGS. 1 and 2
are cross-sectional views illustrating a conventional contact-forming process for an integrated circuit Dynamic Random Access Memory (DRAM) device. As shown in
FIG. 1
, device isolation regions
12
are formed in an integrated circuit substrate, such as a semiconductor substrate
10
, to define active and inactive regions. A plurality of pad electrodes, such as polysilicon pad electrodes
14
, also referred to as poly pads, are formed on the active region of the semiconductor substrate
10
. A first interlayer insulating film
16
is formed on the substrate
10
, including on the poly pads
14
. Bit line electrodes
18
are formed on the first interlayer insulating film
16
over the inactive regions, between the poly pads
14
. The bit line electrodes
18
include a capping layer
20
thereon and a sidewall spacer
21
on the sidewalls thereof. The capping layer
20
and the sidewall spacers
21
may comprise silicon nitride.
A second interlayer insulating film
22
is formed on the first interlayer insulating film
16
including on the bit line electrodes
18
. A photoresist layer pattern
24
is formed on the second interlayer insulating film
22
. Unfortunately, the “proximity effect” may cause the photoresist layer pattern
24
to be uneven, due to the small spacing the pattern. In particular, as shown in
FIG. 1
, the proximity effect may cause an undesired pattern shape
24
′ in the photoresist layer pattern
24
. As is well known to those having skill in the art. The proximity effect occurs when light that is projected through a closely spaced mask pattern overlap and form an unclearly patterned area therebetween.
As shown in
FIG. 2
, contact holes
25
are formed to expose the poly pads
14
by etching the first and second interlayer insulating films
16
and
22
respectively, using the photoresist layer pattern
24
as a mask. Conductive material such as polysilicon is then deposited in the contact holes
25
, to thereby form a storage polysilicon layer
26
.
Unfortunately, as shown in
FIG. 2
, since the photoresist layer pattern
24
is improperly formed over some of the bit line electrodes due to the proximity effect, the photoresist layer pattern
24
exposes portions of the second interlayer insulating film
22
on some of the bit line electrodes. The second interlayer insulating film
22
is thereby etched between the contact holes during the formation of the contact holes
25
. This can result in bridging between the storage polysilicon layers as shown by the dotted circle
28
. This bridging can reduce the reliability and/or yield of the integrated circuits. Moreover, bridging may increase as the integration density of the integrated circuits increases.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming contact holes for integrated circuit devices including integrated circuit memory devices.
It is another object of the present invention to provide methods of forming contact holes that can reduce and preferably eliminate bridging between contact holes.
These and other objects are provided, according to the present invention, by forming a blocking layer pattern on a second interlayer insulating film and then selectively etching first and second interlayer insulating films relative to the blocking layer pattern, to form a plurality of contact holes. The blocking layer pattern can thus provide an etch barrier layer for contact hole formation that can overcome proximity effect limitations, which can thereby prevent bridging between the contact holes.
More specifically, integrated circuit contact holes may be formed on an integrated circuit substrate, by providing a first conductive pattern on the substrate, a first interlayer insulating film on the first conductive pattern, a second conductive pattern on the first interlayer insulating film and a second interlayer insulating film on the second conductive pattern. A blocking layer pattern is formed on the second interlayer insulating film. The blocking layer pattern overlies, is of the same pattern as, and is as least as wide as the second conductive pattern. The first and second interlayer insulating films are then selectively etched relative to the blocking layer pattern and the second conductive pattern, to form a plurality of contact holes that expose the first conductive pattern.
The blocking layer pattern preferably comprises polysilicon and/or silicon nitride. The second conductive pattern preferably comprises a conductive core pattern and a coating on the conductive core pattern. Then, the first and second interlayer insulating films are selectively etched relative to the blocking layer pattern and the coating, to form the plurality of contact holes that expose the first conductive pattern.
A photoresist pattern may also be formed on a portion of the blocking layer pattern. Then, the first and second interlayer insulating films are selectively etched relative to the photoresist pattern, the blocking layer pattern and the second conductive pattern, to form a plurality of contact holes that expose the first conductive pattern.
The photoresist pattern may include a plurality of elongated openings therein. In one embodiment, a respective opening exposes a portion of the blocking layer pattern and extends beyond the exposed portion of the blocking layer pattern. In another embodiment, a respective opening exposes and extends between at least two portions of the blocking layer pattern.
The above-described integrated circuit contact hole forming methods may also be used to form integrated circuit contact holes for integrated circuit memory devices. For integrated circuit memory devices, the first conductive pattern may correspond to a plurality of pad electrodes, the second conductive pattern may correspond to a plurality of bit lines, and capacitor contact plugs may be formed in the plurality of contact holes.
According to another aspect of the present invention, a blocking layer pattern is formed on the second interlayer insulating film that overlies the second conductive pattern. A photoresist is formed on a portion of the blocking layer pattern. The first and second interlayer insulating films are selectively etched relative to the photoresist pattern, the blocking layer pattern and the second conductive pattern to form a plurality of contact holes that expose the first conductive pattern. The composition of the blocking layer pattern and the second conductive pattern, and the openings in the photoresist pattern, may be as described above. This aspect of the present invention may also be used to form integrated circuit memory device contact holes as described above.
Accordingly, the blocking layer pattern can serve as an etch barrier layer for contact hole formation, thereby reducing and preferably preventing bridging between contact holes due to the proximity effect. Moreover, t

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