Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-04
2001-08-14
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06274435
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of fabricating a metal-insulator-metal capacitor, and more particularly, to a method of forming a high capacitance metal-insulator-metal capacitor in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are critical components in the integrated circuit devices of today. Both polysilicon and metal-insulator-metal (MIM) capacitors have been used in the art. The conventional MIM capacitor module which is inserted into the backend process of integrated circuit manufacturing results in a very low capacitance density. The capacitance density is proportional to the reverse of the dielectric thickness. Often, sophisticated additional metal and dielectric layers must be added for high capacitance density.
FIG. 1
illustrates an example of a conventional MIM capacitor process. It is simple, but has a very low capacitance density. Bottom capacitor plate
30
is shown over semiconductor substrate
10
. The metal bottom plate is covered by a thin oxide
32
. Spin-on-glass material
34
fills the gaps between metal lines. A very thick oxide
36
, more than about 1000 Angstroms in thickness and generally a few thousand Angstroms, forms the capacitor dielectric layer underlying the top plate electrode
40
. The thick oxide is required for a low parasitic capacitance between the conducting layers and for good electrical isolation. In this example, the capacitance density F is approximately 10
−17
farads/&mgr;m
2
.
FIG. 2
illustrates an example of another conventional approach in which additional metal and thin oxide layers are added to improve capacitance density. A thin CVD oxide layer
38
is deposited over the bottom plate electrode
30
. This oxide layer
38
has a thickness of approximately a few hundred Angstroms, for example about 500 Angstroms, and forms the capacitor dielectric. The metal layer
42
is formed over the capacitor dielectric. Then the sandwich dielectric layer comprising oxide
44
, spin-on-glass
46
, and oxide
48
, is deposited over the metal layer
42
. An additional metal layer
50
forms the upper plate electrode and contacts the lower metal layer
42
through a via opening. The metal layer
42
for circuit interconnection cannot be used directly as the upper electrode because of the thicker intermetal oxide required thereunder. In this example, the capacitance density F is approximately 6×10
−16
farads/&mgr;m
2
. It is desired to have a capacitance density in the range of 10
−15
to 10
−16
farads/&mgr;m
2
.
U.S. Pat. Nos. 5,576,240 and 5,654,581 to Radosevich et al, U.S. Pat. No. 5,479,316 to Smrtic et al, U.S. Pat. No. 5,708,559 to Brabazon, U.S. Pat. No. 5,406,447 to Miyazaki, U.S. Pat. No. 5,741,721 to Stevens, U.S. Pat. No. 4,959,705 to Lemnios et al, and U.S. Pat. No. 4,971,924 to Tigelaar et al all disclose various methods of forming metal-insulator-metal capacitors. U.S. Pat. No. 5,589,416 to Chittipeddi teaches fabrication of a metal-oxide-polysilicon capacitor. U.S. Pat. No. 5,554,558 to Paterson et al discloses a very high integrity capacitor dielectric in a polysilicon to polysilicon or polysilicon to metal capacitor. U.S. Pat. No. 5,268,315 to Prasad et al teaches silicon nitride as a capacitor dielectric in the fabrication of a MIM capacitor.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for producing a metal-insulator-metal capacitor.
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for producing a metal-insulator-polysilicon capacitor.
Another object of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor having high capacitance density.
A further object is to provide a method for fabricating a metal-insulator-metal or a metal-insulator-polysilicon capacitor having precise capacitor dielectric film control for high capacitance density.
A still further object is to provide a method for fabricating a metal-insulator-metal capacitor or a metal-insulator-polysilicon capacitor having a self-capacitor guard ring as a circuit noise screen.
Yet another object of the invention is to provide a method for fabricating a metal-insulator-metal or metal-insulator-polysilicon capacitor having high capacitance density and low noise.
In accordance with the objects of this invention, a method for fabricating an improved metal-insulator-metal or metal-insulator-polysilicon capacitor having high capacitance density and low noise is achieved. An insulating layer is provided overlying a semiconductor substrate. A capacitor bottom plate electrode is formed overlying the insulating layer. A thin capacitor dielectric layer is deposited overlying the capacitor bottom plate electrode. An etch stop layer is deposited overlying the capacitor dielectric layer. A thick oxide layer is deposited overlying the etch stop layer. The oxide layer over the capacitor bottom plate electrode is etched away stopping at the etch stop layer whereby a recess is formed in the oxide layer overlying the bottom plate electrode wherein sidewalls of the oxide layer overlie the edges of the bottom plate electrode. A capacitor top plate electrode is formed within the recess whereby a guard ring is formed on the sidewalls of the oxide layer within the recess and wherein gaps are left between the capacitor top plate electrode and the guard ring. The top plate electrode is covered with a dielectric layer wherein the gaps are filled by the dielectric layer. A via opening is formed through the dielectric layer to the capacitor top plate electrode and filled with a patterned metal layer to complete formation of a capacitor in the fabrication of an integrated circuit device.
Also in accordance with the objects of the invention, an integrated circuit device with capacitor is described. An interconnection line overlies an insulating layer on a semiconductor substrate. A first dielectric layer overlies the interconnection line wherein the first dielectric layer comprises a capacitor dielectric layer overlying the interconnection line, an etch stop layer overlying the capacitor dielectric layer, and an oxide layer overlying the etch stop layer. A metal line contacts the interconnection line through an opening in the first dielectric layer. The capacitor comprises a capacitor bottom plate electrode overlying the insulating layer on the semiconductor substrate, the capacitor dielectric layer overlying the capacitor bottom plate electrode, the etch stop layer overlying the capacitor dielectric layer, a capacitor top plate electrode overlying the etch stop layer over the capacitor bottom plate electrode within a recess formed in the oxide layer, and a guard ring on the sidewalls of the oxide layer within the recess wherein gaps are left between the capacitor top plate electrode and the guard ring. A second dielectric layer covers the metal line and the top plate electrode wherein the gaps are filled by the second dielectric layer. A patterned metal layer fills a via opening through the second dielectric layer to the capacitor top plate electrode.
REFERENCES:
patent: 4697330 (1987-10-01), Paterson et al.
patent: 4959705 (1990-09-01), Lemnios et al.
patent: 4971924 (1990-11-01), Tigelaar et al.
patent: 5037772 (1991-08-01), McDonald
patent: 5268315 (1993-12-01), Prasad et al.
patent: 5338701 (1994-08-01), Hsu et al.
patent: 5406447 (1995-04-01), Miyazaki
patent: 5449948 (1995-09-01), Inoue et al.
patent: 5479316 (1995-12-01), Smrtic et al.
patent: 5510637 (1996-04-01), Hsu et al.
patent: 5554558 (1996-09-01), Hsu et al.
patent: 5576240 (1996-11-01), Radosevich et al.
patent: 5589416 (1996-12-01), Chittipeddi
patent: 5654581 (1997-08-01), Radosevich et al.
patent: 5708559 (1998-01-01), Brabazon et al.
patent: 5741721 (1998-04-01), Stevens
Ackerman Stephen B.
Lee Calvin
Pike Rosemary L. S.
Saile George O.
Smith Matthew
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