Semiconductor memory device, circuit board mounted with...

Details Semiconductor memory device, circuit board mounted with... Semiconductor memory device, circuit board mounted with...

2000-02-09

2001-03-27

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S063000

Reexamination Certificate

active

06208571

ABSTRACT:

BACKGOUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having a testing function.
The present invention also relates to a circuit board mounted with a semiconductor memory device.
The present invention further relates to a method for testing interconnection between a semiconductor memory device with a circuit board.
2. Description of the Related Art
A mounting density of a printed-wiring board or the like has been increasing due to downsizing of electronic components, and sizes of electronic apparatuses are getting smaller. For example, a package shape of a semiconductor memory device has been reduced from DIP (Dual In-line Package), to SOP (Small Outline Package) and to TSOP (Thin Small Outline Package). Spaces between terminals of semiconductor memory devices are also getting narrower, following downsizing of packages. Recently, CSP (Chip Size Package) in which terminals of a semiconductor memory device are arranged two-dimensionally has been developed.
Connection failures between terminals of electronic components and printed-wiring boards occurring at the time of mounting the electronic components on the boards have been increasing with downsizing of packages. And it is getting much more difficult to directly confirm an interconnection between a terminal and a printed-wiring board. For this reason, an interconnection testing method for easy and secure confirmation of a connection between an electronic component and a printed-wiring board mounted with the component has been desired.
As such a method, a boundary scanning method has been known. The boundary scanning method is a testing method standardized as IEEE/ANSI Standard 1491.1.
FIG. 1
is a block diagram showing an outline of the boundary scanning method.
A TDI (Test Data Input) terminal, a TMS (Test Mode Select) terminal, a TCK (Test Clock) terminal, and a TDO (Test Data Output) terminal are formed in each of electronic components
1
a
and
1
b
, and on a printed-wiring board
2
. The TDI, TDO, TCK and TMS terminals are terminals dedicated to testing, and not used for other purposes. Each of the testing terminals of the electronic components
1
a
and
1
b
is connected to each of the corresponding testing terminals according to a wiring pattern
3
formed on the board
2
.
A plurality of BS cells
4
, an instruction register
5
, a bypass register
6
, and a TAP controller
7
are implemented in both of the electronic components
1
a
and
1
b
, as a testing circuit. The BS cells
4
are arranged in the electronic components
1
a
and
1
b
, corresponding to respective terminals T connected to a core unit
8
, and have a latching function. The instruction register
5
is a circuit for storing an instruction for testing received by the TDI terminal. The bypass register
6
is a circuit for directly outputting data received by the TDI terminal to the TDO terminal. The TAP controller
7
has a function of decoding a test-mode signal received by the TMS terminal.
When a plurality of electronic components such as the electronic components
1
a
and
1
b
are mounted on the printed-wiring board
2
as shown in
FIG. 1
, the TDO terminal of the electronic component
1
a
is connected to the TDI terminal of the neighboring electronic component
1
b
. A scanning path PATH on a loop shown by thick solid lines is formed on the board
2
.
An interconnection test is performed on the electronic components
1
a
and
1
b
and on the board
2
in the following manner. A controller (not shown in
FIG. 1
) connected to the external of the board
2
feeds a testing instruction and an input pattern from the TDI terminal to the electronic components
1
a
and
1
b
, by controlling each of the above terminals. Each of the testing circuits
4
,
5
,
6
, and
7
of the electronic components
1
a
and
1
b
operates in accordance with the instruction and the input pattern from the controller, and outputs an output pattern from the TDO terminal.
The controller confirms a connection between each of the terminals T of the electronic components
1
a
and
1
b
and the printed-wiring board
2
, by comparing the output pattern with expected values. Faults such as a soldering failure of each terminal and slight displacement of mounted position of the electronic components
1
a
and
1
b
can be detected.
The boundary scanning method needs terminals dedicated to testing and a plurality of testing circuits within an electronic component. Therefore, application of the boundary scanning method substantially affects chip sizes. For this reason, this method is mainly applied to logic products such as microprocessors and ASICs (Application Specific ICs).
Meanwhile, as a method of testing interconnections for semiconductor memory devices or the like, SCITT (Static Component Interconnection Test Technology) has been developed. Hereinafter, an example of an SDRAM (Synchronous DRAM) to which the SCITT method has been applied will be explained.
An SDRAM of this kind has a mode for testing interconnections, in addition to a normal operation mode. A shift to the connection testing mode is performed by feeding a predetermined signal to a predetermined terminal before a power-on sequence is performed. A semiconductor memory device operating in synchronization with a clock, such as an SDRAM, can easily distinguish internal circuit control at the time of the power becomes ON from normal operation control. Therefore, an erroneous shift to the connection testing mode during a normal operation is prevented by controlling a shift to the testing mode only at the time the power becomes ON.
During the connection testing mode, each terminal of the SDRAM, except for terminals used as control terminals, is used either as an inputting test terminal feeding an input pattern or as an outputting test terminal outputting an output pattern. For this reason, terminals dedicated to testing are not necessary in the SCITT method. In an SDRAM, a simple operation circuit carrying out a logic operation on input patterns and outputting a result of the operation as an output pattern is implemented. However, a scale of the circuit necessary for testing interconnection is smaller than the boundary scanning method.
In the SCITT method described above, a memory controller, for example, mounted on a printed-wiring board together with an SDRAM feeds an input pattern to the inputting test terminal of the SDRAM. The SDRAM carries out a logic operation and outputs a result of the operation as an output pattern. The memory controller compares the output pattern with expected values and confirms an interconnection between each of the terminals in the SDRAM and the board. In this manner, faults such as a soldering failure of a terminal and slight displacement of mounted position of a chip can be detected.
The SCITT method can detect a connection failure for all terminals except for power supply terminals, a ground terminal, and a control terminal for testing. The faults which can be detected are stuck-at 0 failures, stuck-at 1 failures, open failures, and 2-net AND-type and OR-type short failures.
As has been described above, the SCITT method does not need dedicated testing terminals and the scale of the circuit necessary for testing is smaller than in the boundary scanning method. Therefore, the chip size is not affected by application of the SCITT method.
In order to carry out the boundary scanning method described above, the TDI terminals, the TMS terminals, the TCK terminals, and the TDO terminals dedicated to testing are formed in the electronic components
1
a
and
1
b
, and the testing circuits such as the instruction register
5
and the TAP controller
7
are implemented. Therefore, the chip sizes of the electronic components
1
a
and
1
b
increase. Since an increase in a chip size directly affects production costs, application of the boundary scanning method to a semiconductor memory device, such as a DRAM, especially, has been difficult.
The SCITT method described above

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