Static information storage and retrieval – Read/write circuit – Testing
Patent
1989-03-07
1991-02-12
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Testing
365200, 365193, 36523002, 371 211, G11C 700
Patent
active
049929852
ABSTRACT:
An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals with the write enable signal, which signal level combinations correspond to those which are otherwise left unused in the normal operating mode thereby obviating the requirement of an additional external control signal terminal. Such initiating of the test mode can be effected by setting the RAS signal of the DRAM at a logic "low" level when the CAS signal and the WE signal are at a logic "low" level. Clearing or resetting thereof is effected by the same combination sequence, except that the WE signal is at a logic "high" level. The setting or initiating of a test mode is also implemented by the additional combination of one of the row address signal bits, e.g. the most significant bit.
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Mitsubishi Giho, vol. 59, No. 9, Mitsubishi Electric Corp., 1985.
Etoh Jun
Kimura Katsutaka
Miyazawa Kazuyuki
Shimohigashi Katsuhiro
Garcia Alfonso
Hitachi , Ltd.
Popek Joseph A.
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