Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-27
2001-06-26
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S263000, C438S264000
Reexamination Certificate
active
06251727
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an improved method for making split-gate non-volatile memory (NVM). More specifically, the present invention relates to an improved method for making split-gate type non-volatile memory cells wherein the select gate is self-aligned relative to the floating gate, so as to eliminate the misalignment problems, while allowing a further down-scaling of the memory cells without the need to incur large capital expenses for upgrading existing photolithography equipment.
BACKGROUND OF THE INVENTION
Due to their relatively small dimension, non-volatile memory cells, or non-volatile electrically alterable semiconductor memory derives, are well-known in the art and have become an important everyday consumers item. Typically, electrical alterability is achieved by the so-called Fowler-Nordheim tunneling of charges between a floating gate (i.e., without connecting to any conductive element) and the silicon substrate through a very thin dielectric. Each storage cell requires a floating gate and a select gate. The degree of misalignment of the select gate relative to the floating gate is one of the major factors that can significantly and adversely affect the performance of a split gate non-volatile memory cell. A non-self-alignment split-gate process must take the alignment tolerance into consideration. If the degree of misalignment exceeds the alignment tolerance, many undesirable cell characteristics can surface. Some of the typical problems include unsatisfactory program efficiency, assymmetric cell current, poor immunity to drain disturb during programming, etc.
U.S. Pat. No. 5,280,446 provides a concise background information about the conventional “stacked”-type flash EPROM device and the problems associated therewith. The flash memory cell circuit disclosed in the '446 patent comprises a plurality of memory elements in a matrix fashion with each element including a semiconductor substrate, a drain region, a source region, a floating gate, a control gate, and a select gate. A special arrangement on the memory array is provided such that the programming of the memory cell is achieved by high efficient hot electron injection which allows lower drain voltage during programming, so as to achieve low voltage power supply operation capability.
U.S. Pat. Nos. 5,029,130, 5,045,488, and 5,067,108 disclose a single transistor electrically programmable and erasable memory cell having a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is provided over the source, channel and drain regions, and a floating gate is positioned on top of the channel region and over a portion of the drain region. A second insulating layer is provided which has a top wall over the floating gate and a side wall adjacent thereto. A control gate has a first portion over the first insulating layer and a second portion over the top wall of the second insulating layer and over the floating gate. The control gate is not self-aligned to the floating gate, and many misalignment problems can be experienced.
U.S. Pat. No. 5,674,767 discloses a method of manufacturing a nonvolatile memory device having a self-aligned structure. The flash memory device has a split gate structure, and the method includes the steps of forming a gate insulating film on a semiconductor substrate. A semiconductor layer is formed on the gate insulating film and etched to form floating gates and a semiconductor pattern between the floating gates. Impurity ions are implanted into the same side of the substrate as the floating is formed, to form a drain region. A planarizing film is deposited on the substrate and etched until the upper surfaces of the floating gates and the semiconductor pattern are exposed. The semiconductor pattern is removed and impurity ions are implanted into the substrate to form a source region. The planarizing film is removed to expose the floating gate, and a dielectric film is formed thereon. Finally, a control gate is formed on the substrate. The method disclosed in the '767 patent provides a means for self-alignment of the floating gate with respect to the source/drain impurity regions, misalignment problems still exist between the control gate and the floating gate.
U.S. Pat. No. 5,330,938 discloses a method of making non-volatile split gate EPROM memory cell and self-aligned field insulation. The memory cell comprises a substrate with diffusion of source and drain separated by a channel area, a floating gate superimposed over a first part of the channel area and a control gate formed by first and a second polysilicon strip, respectively, a cell gate oxide between the floating gate and the first part of the channel area, an interpoly oxide between the floating gate and the control gate, and a layer of dielectric film. The floating gate is aligned with the drain diffusion, and the control gate is aligned with the floating gate and with the diffusion of source and drain. However, the method disclosed in the '938 is relatively complicated for implementation and can significantly increase manufacturing cost, and is inapplicable when the control gate has a peripheral length that extends beyond the floating gate.
SUMMARY OF THE INVENTION
The primary object of the present invention is to develop a non-volatile memory cell with minimized misalignment between the select gate and the floating gate. More specifically, the primary object of the present invention is to develop an improved method for making split-gate type non-volatile memory cells wherein the select gate is self-aligned relative to the floating gate, so as to eliminate the misalignment problems, while allowing a further down-scaling of the memory cells without the need to incur large capital expenses for upgrading existing photolithography equipment.
The method disclosed in the present invention can be summarized as generally comprising the following steps:
(1) Forming a tunnel oxide on a substrate.
(2) Depositing a poly-1 layer (i.e, the first polysilicon layer) on the tunnel oxide layer followed by doping.
(3) Depositing a nitride layer on the poly-1 layer.
(4) Depositing and developing a nitride photoresist using a nitride photomask which exposes areas intended to encompass floating gate and cell drain.
(5) Applying a first nitride etching to partially etch the nitride layer, then removing the nitride photoresist.
(6) Depositing and developing a poly-1 photoresist using a poly-1 photomask which exposes the previously etched nitride layer and a predetermined portion of the un-etched nitride layer adjacent thereto.
(7) Applying a second nitride etching to further etch the previously etched nitride layer and the adjacent un-etched nitride layer until the portion of the poly-1 layer underlying the etched nitride layer is exposed, then removing the photoresist.
(8) Using the nitride layer as a mask to cause oxidation in the poly-1 layer and form a poly-oxide layer. It should be noted that with the stepped nitride layer construction of the present invention, the cell drain portion has already been marked, or self-aligned, when the entire nitride layer is utilized as the mask during poly-1 oxidation.
(9) Depositing and developing a cell drain photoresist using a cell-drain photomask, followed by a third nitride etching, a poly-1 etching, drain implantation, and removal of photoresist.
(10) Optionally, a drain oxidation step can be applied before the photoresist removal to increase the oxide layer thickness above the drain.
(11) Removing the nitride layer using hot H
3
PO
4
or wet etch.
(12) Etching the poly-1 layer using the poly-oxide layer as a hard mask.
(13) Forming a sidewall dielectric layer around the remaining poly-1 layer by dielectric deposition or dielectric growth.
(14) Depositing a poly-2 layer (i.e, the second polipilicon layer) on the wafer followed by doping.
(15) Depositing and developing a poly-2 photoresist using a poly-2 photomask which will cover the portion of the poly-2 layer intended to be select gate, followed by etching the poly-2
Liauh W. Wayne
Smith Matthew
Winbond Electronics Corp
Yevsikov V.
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