Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-17
2001-01-30
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000
Reexamination Certificate
active
06180456
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention generally relates to non-volatile memory cells and more particularly to a three-dimensional, direct-write non-volatile random access memory (NVRAM) cell having a high integration density and fabrication methods thereof.
BACKGROUND DESCRIPTION
Non-volatile floating gate memory cells, such as in a non-volatile random access memory (NVRAM) arrays are well known in the industry. In NVRAM cells, the cell's conductive state is determined by the charge state of the cell's floating gate. The floating gate is an electrically isolated gate of a field effect transistor (FET) stacked in a two device NAND-like structure. Charge is forced onto or removed from the floating gate through a thin insulator layer that, normally (during a read operation), isolates the gate electrically from other adjoining conductive layers. Typically, a negatively charged floating gate is representative of a binary one state, while an uncharged floating gate is representative of a binary zero state. The other device in the NAND-like structure provides cell read and write selection.
For writing cells, a control gate (or program gate) is capacitively coupled to the floating gates in a portion of an array. A program voltage that is much higher than normal operating voltages, is placed on a control gate to bias the cell's floating gate sufficiently to change the charge on the cell's floating gate, i.e., to write selected cells.
However, typical program voltages, which range from 8-20 volts, are sufficiently high to destroy single gate FETs. Consequently, NVRAM chips require inclusion of special high voltage devices capable of handling these higher voltages without damage. Typical high voltage FETs have thicker gate oxides that are capable of withstanding the higher electric fields developed FETS by the presence of the programming voltage.
Typically, areas of the particular chip die were defined, lithographically. Unfortunately, exposing the thicker dielectric in these high voltage device areas to lithographic processing degraded the dielectric, causing failures, which degraded chip yield and, left residual contaminants that made these prior art devices less reliable.
Thus, there is a need for a semiconductor process for non-volatile memory wherein these gate oxide FETs may be included without degrading chip yield or reliability.
SUMMARY OF THE INVENTION
It is a purpose of the present invention to reduce NVRAM cell size, and therefore increase the number of NVRAM cells that may be included on a single integrated circuit chip.
The present invention is a logic chip including a non-volatile random access memory (NVRAM) array and method of fabrication thereof. The chip includes devices with gates on one or more of three polysilicon layers. Chip logic uses normal FETs and array support includes high voltage FETs. Both logic and support are CMOS. The gates of normal FETs in the chip logic are fashioned from the third or uppermost polysilicon layer. The third polysilicon layer also is used as a mask for high voltage FETs and array word lines, both of which use the second polysilicon layer for gates. The first polysilicon layer is used solely for cell floating gates.
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Lam Chung Hon
Miles Glen L.
Nakos Jame Spiros
Willets Christa R.
Booth Richard
International Business Machines - Corporation
McGuireWoods LLP
Sabo William D.
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