Method of forming dual metal gate structures or CMOS devices

Details Method of forming dual metal gate structures or CMOS devices Method of forming dual metal gate structures or CMOS devices

2000-02-08

2001-09-18

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S584000

Reexamination Certificate

active

06291282

ABSTRACT:

CROSS-REFERENCE TO RELATED PATENT/PATENT APPLICATIONS
The following commonly assigned patents and patent applications are hereby incorporated herein by reference:
Pat. No./Ser. No.
Issue/Filing Date
TI Case No.
6,063,677
5/16/2000
TI-22027
6,063,675
5/16/2000
TI-22748
09/396,642
9/15/1999
TI-24776
FIELD OF THE INVENTION
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of fabricating a metal gate structures for CMOS devices.
BACKGROUND OF THE INVENTION
As electronic devices become more and more complex, the need for greater and greater numbers of transistors on the device is increased. In addition, power consumption needs to be reduced while the speed of the devices needs to be increased. At least part of the answer to these requirements involves reducing the area that each transistor occupies. However, this may adversely affect one or more of the other requirements. More specifically, as the transistors are scaled down, the gate structure is also scaled down and this increases the resistance of the gate. Hence, the power consumption is increased and the speed of the device is decreased.
Several attempts to reduce the sheet resistivity of the gate structures have been made in the past. First, the polycrystalline silicon was more heavily doped with either n-type or p-type dopants. Then, the upper portion of the gate was silicided with tungsten or titanium. Presently, cobalt silicide is being used so as to reduce the resistivity for smaller geometries. The next likely solution will involve metal gate structures.
Metal gate structures provide lower sheet resistivity virtually irrespective of the width of the gate. However, many metal gate materials have problems which must be overcome before they can be implemented in a standard semiconductor processing flow. One problem is that many metals are unstable next to SiO
2
, which is commonly used for the gate dielectric layer. Another problem is that many metals become less conductive when they are oxidized.
Aluminum and tungsten have been used to form gate structures. Aluminum may not be a good choice due to the problems stated above and tungsten has a work function which lies between the work function of p-type polycrystalline silicon (poly) and n-type poly. A problem with tungsten, though, is that as the applied voltages become smaller and smaller the fact that the work function is midgap and is unchangeable (as compared to n-type and p-type poly), it may become difficult to provide a gate potential greater than the threshold voltage of the PMOS and NMOS device.
In an attempt to over come this threshold voltage problem using one midgap metal for both PMOS and NMOS device, aluminum has been utilized for one type of devices while platinum is used for the other type of devices. However, platinum is expensive and difficult to work with and aluminum suffers from the problems listed above. Hence, a need exists for a gate electrode material whose conductivity is not relative to the gate width and which has different work functions for PMOS devices and NMOS devices.
SUMMARY OF THE INVENTION
An embodiment of the instant invention is a method of forming a first transistor having a first gate electrode and a second transistor having a second gate electrode on a semiconductor substrate, the method comprising the steps of: forming a first conductive material insulatively disposed over a first portion of the semiconductor substrate, the first conductive material having a first work function; forming a second conductive material insulatively disposed over a second portion of the semiconductor substrate, the second conductive material is comprised of the first conductive material but has a second work function which is different than the first work function; and wherein the first conductive material is used to form the first gate electrode and the second conductive material is used to form the second gate electrode. In one alternative embodiment, the first conductive material is comprised of Ta and the second conductive material is comprised of Ta
x
N
y
. In another alternative embodiment, the first conductive material is comprised of Mo and the second conductive material is comprised of Mo
x
N
y
. In yet another alternative embodiment, the first conductive material is comprised of Ti and the second conductive material is comprised of Ti
x
N
y
.
Another embodiment of the instant invention is a method of forming a first transistor having a first gate electrode and a second transistor having a second gate electrode on a semiconductor substrate, the method comprising the steps of: forming a conductive material insulatively disposed over the semiconductor substrate, the conductive material having a work function; and altering a portion of the conductive material so as to change the work function of the altered conductive material, the conductive material to form the first gate electrode and the altered conductive material to form the second gate electrode. Preferably, the first transistor is an NMOS device, the second transistor is a PMOS device, and the first transistor and the second transistor form a CMOS device. The conductive material is, preferably, comprised of a conductor selected from the group consisting of: Ta, Mo, Ti and any combination thereof. Preferably, the step of altering a portion of the conductive material is comprised of: subjecting the portion of the conductive material to a plasma which incorporates a nitrogen-containing gas.


REFERENCES:
patent: 6027961 (2000-02-01), Maiti et al.
patent: 6043157 (2000-03-01), Gardner et al.
patent: 6066533 (2000-02-01), Yu
patent: 6130123 (2000-10-01), Liang et al.

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