Method of forming a split gate flash memory cell

Details Method of forming a split gate flash memory cell Method of forming a split gate flash memory cell

2000-06-01

2001-06-05

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000

Reexamination Certificate

active

06242309

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a flash memory cell on a semiconductor wafer, and more particularly, to a method of forming a split gate flash memory cell of a non-volatile memory on a semiconductor wafer.
2. Description of the Prior Art
Non-volatile memory, such as an erasable and programmable read only memory (EPROM), electrically erasable programmable read only memory (E
2
PROM) and flash memory, all store data regardless of whether or not electrical power is supplied, and read and write data by controlling a threshold voltage of a control gate. Conventionally, non-volatile memory is designed as a stack-gate. The stack-gate comprises a floating gate for storing charge, an ONO (oxide-nitride-oxide) dielectric layer and a control gate for reading and writing of the data. Like a capacitor storing data, the memory stores charge in the stack-gate to represent a “1”, and erases the charge from the stack-gate to represent a “0”. Additionally, the data stored in memory is changed by applying extra energy to the stack-gate.
Please refer to
FIG. 1
to FIG.
4
.
FIG. 1
to
FIG. 4
are cross-sectional diagrams of forming a split gate flash memory cell on a semiconductor wafer
10
according to the present invention. As shown in
FIG. 1
, the semiconductor wafer
10
comprises a silicon substrate
12
and a silicon oxide layer
14
positioned on the silicon substrate
12
.
Please refer to
FIG. 2. A
patterned photoresist layer
16
is first formed on the surface of the silicon oxide layer
14
. An ion implantation process is then performed, using the photoresist layer
16
as a hard mask, to form two doped regions on the surface of the silicon substrate
12
. A rapid thermal process (RTP) is later used later to drive the dopants into the silicon substrate
12
to form two diffused regions
22
. The diffused regions
22
serve as a source and a drain of a split gate, and the silicon substrate
12
between the two diffused regions serves as a channel of the split gate.
Please refer to FIG.
3
. The photoresist layer
16
is removed and a low pressure chemical vapor deposition (LPCVD) process is performed to form a polysilicon layer (not shown). A patterned photoresist layer
26
is then formed on the surface of the polysilicon layer. An anisotropic etching process is performed, using the photoresist layer
26
as a hard mask, to vertically remove the polysilicon layer down to the surface of the silicon oxide layer
14
to form a floating gate
24
of the split gate flash memory cell.
Please refer to FIG.
4
. The photoresist layer
26
is removed and an LPCVD process is performed to form a silicon oxide layer
28
uniformly on the surface of the semiconductor wafer
10
. Another LPCVD process is then performed to form a polysilicon layer (not shown) on the surface of the silicon oxide layer
28
and a photoresist layer is formed on this polysilicon layer. An anisotropic process is then performed, using the photoresist layer as a hard mask, to vertically remove the polysilicon layer down to the surface of the silicon oxide layer
28
to form the control gate
30
of the split gate flash memory cell. The silicon oxide layer
28
serves as a tunnel oxide layer of the split gate flash memory cell.
The dimensions of the channel
20
(represented by “a” in
FIG. 4
) are determined by the dimensions of the floating gate
24
(represented by “c” in FIG.
4
), the dimensions of the controlling gate
30
(represented by “b” in
FIG. 4
) and the overlapping regions of the controlling gate
30
with the floating gate
24
. Because the dimensions of the channel
20
are simultaneously influenced by three factors, it is difficult to control the dimensions of the channel
20
during the formation of the split gate cell.
The positions of the source and the drain change during the fabrication of the split gate cell due to inaccuracies when aligning the photo mask. This results in the formation of a shorter channel of the split gate cell that usually causes punch through of the drain and the source, reducing the electrical performance of the split gate memory cell.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a split gate memory cell with a self-aligned source and drain on a semiconductor wafer that solves the above-mentioned problems.
In a preferred embodiment, the present invention provides a method of forming a split gate memory cell with a self-aligned source and drain on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, at least two floating gates on the surface of the silicon substrate, and a silicon nitride layer on each floating gate. The method of the present invention first forms a photoresist layer on the surface of the silicon substrate and a lithographic process is then performed to remove a portion of the photoresist layer between the floating gates. A first ion implantation process is performed, using the photoresist layer and the silicon nitride layer on the floating gate as hard masks, to form a drain in the silicon substrate between the floating gates. After the photoresist layer is removed, a passivation layer is formed on the surface of the silicon substrate. The passivation layer covers the silicon substrate and the top surface and the walls of the floating gate. An etching process is performed to form a spacer around each floating gate. The spacers between the floating gates are joined and cover the drain. Finally, a second ion implantation process is performed, using the spacers as a hard mask, to form a drain.
It is an advantage of the present invention that the positions of the source and the drain are self-aligned to the floating gate of the split gate. The present invention performs ion implantation processes, using the silicon nitride layer on each floating gate as a hard mask, to form the drain on the silicon substrate, and uses the spacers around the floating gate as a hard mask, to perform another ion implantation process to form the source. Thus, the source and the drain are self-aligned to the floating gate and the dimensions of the channel of the split gate are accurately controlled. Since this effectively prevents changes of the channel length due to inaccuracies when aligning the photo mask, punch through issues of the drain and the source are thus avoided, ensuring the electrical performance of the split gate memory cell. Additionally, the present invention forms the source and the drain using two ion implantation processes. Hence, the dosage of the source and the drain can be flexibly changed according to manufacturing conditions.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5856224 (1999-01-01), Sheu
patent: 6013552 (2000-01-01), Oyama
patent: 6143606 (2000-11-01), Wang et al.

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