Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-21
2001-09-04
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S301000, C438S303000
Reexamination Certificate
active
06284610
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of silicidation wherein silicon stress is reduced in the fabrication of integrated circuits.
(2) Description of the Prior Art
Many benefits derive from silicided polysilicon gates and source/drain junctions. Nevertheless, recent investigations indicate that abnormal compressive stresses can be generated within the silicon substrate at the source/drain regions, especially near the shallow trench isolation (STI) corner or beneath the spacers during silicidation. These deleterious compressive stresses readily create defects at or in the vicinity of the interface between silicide and silicon. These defects have been diagnosed as the main culprit for high leakage current in the case of titanium silicidation. In addition, the compressive stresses induce the generation of high tensile stress within proximity regions, e.g. beneath the gate. The level of the tensile stress increases with the shrinking of gate length. Hence, the concomitant compressive stresses from source/drain silicidation have to be remedied effectively as well as efficiently.
FIG. 1
illustrates a portion of a partially completed integrated circuit. The semiconductor substrate
10
is preferably composed of silicon having a (100) crystallographic orientation. Gate electrode
16
and source/drain region
20
are formed in and on the semiconductor substrate as is conventional in the art. The source/drain junction has been silicided
22
. The circles
23
indicate defects; leakage paths beneath the spacers and around the shallow trench isolation (STI). These are localized stress junctions. Stress junctions occur in regions where compressive stress from silicidation at the source/drain junction meets tensile stress at the spacer and the STI.
U.S. Pat. No. 5,683 924 to Chan et al teaches formation of a silicide film over epitaxial silicon or polysilicon raised source/drain regions. U.S. Pat. No. 6,001,697 to Chang et al discloses poly plugs over the source/drain junctions where silicidation is performed over the poly plugs. U.S. Pat. No. 5,879,997 to Lee et al discloses a polysilicon layer over the source/drain regions. The polysilicon is oxidized. Silicidation is not disclosed. U.S. Pat. No. 6,004,879 to Hu et al teaches a CoSixO contact material. None of the patents discuss stress relief during silicidation.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of siliciding gates and source/drain junctions in the fabrication of an integrated circuit.
A further object of the invention is to provide a method of siliciding source/drain junctions wherein compressive stress generated beneath the silicided source/drain junctions is reduced.
Yet another object is to provide a method of siliciding source/drain junctions wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon.
Yet another object is to provide a method of siliciding source/drain junctions wherein compressive stress of the underlying silicon is avoided by the insertion of an oxide buffer layer between the silicide and the silicon.
In accordance with the objects of the invention a method for siliciding source/drain junctions is achieved wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A gate electrode and associated source/drain extensions are provided in and on a semiconductor substrate. A buffer oxide layer is deposited overlying the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. The polysilicon layer will form the source/drain junctions and silicon source. The source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during the siliciding.
Also in accordance with the objects of the invention, a method for siliciding source/drain junctions is achieved wherein compressive stress of the underlying silicon is avoided by the insertion of a buffer layer between the silicide and the silicon. A polysilicon gate electrode and associated source/drain junctions are provided in and on a semiconductor substrate. A first nitride layer overlies a top surface of the polysilicon gate electrode. A thermal oxidation forms oxide sidewalls on the polysilicon gate electrode and a first oxide layer over the substrate. A buffer oxide layer is deposited overlying first oxide layer on the semiconductor substrate and the gate electrode. A polysilicon layer is deposited overlying the buffer oxide layer. A second nitride layer is deposited overlying the polysilicon layer. The nitride layer is polished back until the buffer oxide layer overlying the gate electrode is exposed whereby a vertical portion of the polysilicon layer is exposed adjacent to the buffer oxide layer forming a vertical sidewall on the gate electrode. The exposed polysilicon layer is etched away thereby exposing a portion of the buffer oxide layer overlying the source/drain junction. The exposed buffer oxide layer overlying the semiconductor substrate and overlying the gate electrode are etched away thereby exposing a portion of the semiconductor substrate and exposing the first nitride layer of the gate electrode. Thereafter an epitaxial-silicon layer is grown overlying the exposed semiconductor substrate. The first and second nitride layers are removed. The gate electrode and source/drain junctions are silicided whereby the buffer oxide layer provides compressive stress relief during siliciding to complete siliciding of the source/drain junctions in the fabrication of an integrated circuit device.
REFERENCES:
patent: 5683924 (1997-11-01), Chan et al.
patent: 5879997 (1999-03-01), Lee et al.
patent: 6001697 (1999-12-01), Chang et al.
patent: 6004879 (1999-12-01), Hu et al.
patent: 6177314 (2001-01-01), van der Meer et al.
patent: 6215152 (2001-04-01), Hebert
patent: 7201777 (1995-08-01), None
patent: 10125623 (1998-05-01), None
Cha Randall Cher Liang
Chan Lap
Chua Chee Tee
Pey Kin Leong
Bowers Charles
Chartered Semiconductor Manufacturing Ltd.
Nguyen Thanh
Pike Rosemary L. S.
Saile George O.
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