Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
1999-12-08
2001-09-11
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S189050, C365S233100
Reexamination Certificate
active
06288953
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a semiconductor memory device, more particularly to a sense amplifier control circuit, responsive to an output generated from an address transition detection circuit, for generating multiple signals to control sense amplifiers in a semiconductor memory device.
DESCRIPTION OF THE RELATED ART
Higher density memory devices usually employed address transition detection (ATD) circuits which generate signals active when external addresses are being changed. A signal made by the ATD circuit is used in controlling and adjusting operations of sense amplifiers, such as initiating a starting point of a sensing cycle and for establishing periods of the sensing, precharging, discharging, and equalizing cycles. It is important to optimize the generation of signals for controlling the sense amplifiers and to set activating conditions of the signals in a high density memory device, in order to accomplish an efficient read-out operation without failure.
As shown in
FIG. 1
, a general semiconductor memory device (e.g., usually asynchronous semiconductor memory device) includes a memory cell array
100
; a row decoder
110
for selecting wordlines of the memory cell array; a column decoder
120
for selecting bitlines of the memory cell array, an X/Y predecoder
130
for connecting external address lines Ai to the row and column decoders; an ATD circuit
140
for detecting a variation of the external address; a sense amplifier control circuit
150
for receiving a master signal MS from the ATD circuit and for generating sense amplifier control signals SACi and sense amplifier latch control signal SAL; a sense amplifier circuit
160
for detecting data stored in memory cells of the memory cell array is response to control signals SACSi and SAL supplied from the sense amplifier control circuit; and a data buffer
170
for transferring sensed data from the sense amplifier circuit to output terminals of the memory device.
The ATD circuit
140
, with reference to
FIG. 2
, is formed of a summator
10
, noise filter
12
and pulse generating circuits
14
,
16
,
18
,
20
, and
22
which respectively generate signals SACS
1
, SACS
2
, SACS
3
, SAL, and SACS
4
. Summator
10
receives short pulse signals SPi each of which is correspondingly dependent on a variation of the corresponding address signals, and then generates a summation signal SUM which reflects the time variation or variance of the external address signals Ai. The SUM signal is applied to the noise filter
12
which generates a master signal MS to be applied to pulse generation circuits
14
,
18
, and
22
. Pulse generation circuit
14
makes a sense amplifier control signal SACS
1
from master signal MS. Pulse generation circuit
16
receives the control signal SACS
1
, and then produces a sense amplifier control signal SACS
2
. Pulse generation circuit
18
receives the MS and SACS
2
signals, and then generates SACS
3
. Pulse generation circuit
20
receives SACS
3
signals, and then outputs sense amplifier latch control signal SAL. Pulse generation circuit
22
receives MS and SAL, and then generates SACS
4
.
In
FIG. 3
, which is a timing diagram corresponding with
FIG. 2
, if summation signal SUM is applied to noise filter
12
with a normal pulse shape A, sense amplifier control signals SACS
1
-SACS
4
and latch control signal SAL are generated from their corresponding circuits shown in
FIG. 2
, enabling a successful sensing operation to be conducted in the sense amplifier circuits. However, it may occur that, if summation signal SUM has a defective (or distorted) pulse shape like B, due to an influence of noise, in which the pulse width is shorter than the normal one (A) and a lower peak voltage, SACS
1
is generated with a shorter pulse width than its normal width, as shown by the broken line (this in
FIG. 3
denotes an abnormal case for the defective SUM) even through SUM passes through noise filter
12
. Thus, SACS
2
is abnormally activated at an earlier time and with a shorter pulse width, and, subsequently the falling edge of SACS
3
is forced to be faster than the normal one (as shown by the solid line). Thereby, latch control signal SAL is activated at a time earlier than that of the normal case, causing an activation period of SACS
4
to be shorten thereby. Those earlier activations and shorter pulse widths for the control signals cannot provide an enough time in a complete sensing operation to the sense amplifier which needs a predetermined period for detecting a data level of a memory cell. As a result, it would be easy to induce reading failures from the abnormal fluctuation with the sense amplifier control signals and latch control signals.
SUMMARY OF THE INVENTION
The present invention is intended to solve the problems. And, it is an object of the invention, to provide a semiconductor memory device capable of securing a reliable sensing operation even in an existence of input noise.
It is an object of the invention to provide a semiconductor memory device for externally generating normal control signals for controlling a sense amplifier.
It is another object of the invention to provide a semiconductor memory device capable of internally generating sense amplifier control signals even when an input signal thereinto is supplied from an ATD circuit with noise.
In order to accomplish those objects, a memory of this invention includes a circuit for generating a plurality of control signals for sense amplifiers and sense amplifier latch circuits, and a circuit for inhibiting a generation of a control signal which causes a transfer from the sense amplifier to a data output buffer. An invalid data transfer through the latch circuit can be prevented from a noise-included address transition signal.
REFERENCES:
patent: 5566112 (1996-10-01), Lysinger
patent: 5598371 (1997-01-01), Lee et al.
Le Vu A.
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
LandOfFree
Semiconductor memory device having sense amplifier control... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device having sense amplifier control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having sense amplifier control... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2534483