Method to fabricate DRAM capacitor

Details Method to fabricate DRAM capacitor Method to fabricate DRAM capacitor

1999-09-10

2001-03-13

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S240000, C438S261000, C438S287000, C438S386000

Reexamination Certificate

active

06200852

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory process, and more specifically, to a method of fabricating DRAM capacitors using multiple thin silicon nitride layers as the capacitor dielectric layer.
BACKGROUND OF THE INVENTION
The computer and electronics industry demand of increasing its whole speed performance as well as its cost down for fabricating integrated circuits. As far as a computer is concern, it is without doubting that the DRAM integrated circuits plays a crucial role because it is used by a large number and it plays a vital factor for determining the I/O speed in a computer. Hence, pursuing the miniaturization of the DRAM device as well as high-speed performance are almost the ultimate goals.
For pursuing high-speed requirement, the DRAM cell's storage capacity is an important factor to be considered. The capacitor is formed with a storage node, a cell plate, and an intervening dielectric layer. Thus the storage capacity could be increased by making the capacitor dielectric layer thinner, by using an insulator with a large r dielectric constant, or by increasing the area of the capacitor. The first two options are not viable, since capacitor dielectric layers thinner than those now being used in DRAM cells will suffer leakage current due to Fowler-Nordheim tunneling. Moreover, it will also deteriorate the oxidation resist. However, the suffering from a higher leakage current for using a larger dielectric constant layer is being reported in some research. Thus, most approach is by means of increasing the surface area of the bottom cell plate. For instance, the crown-shaped capacitor or fin shaped capacitor or the cylindrical shaped capacitor so as to increase the capacitance. The integrity of about 256M or 1 Giga bytes DRAM capacitor in a chip, the present design rule is, however, can not be satisfied when utilizes merely by increasing the surface area of the bottom cell plate. The lithographic and etching issues are suffered due to the high aspect ratio of the contact hole.
Thus, improving the effective dielectric constant of the capacitor dielectric layer without the leakage current issue to obtain the large capacitance may be the best approach to alleviate the burden of the lithographic and etching technique
The present invention provides such a method.
SUMMARY OF THE INVENTION
A method is disclosed for fabricating a DRAM cell, which has a capacitor dielectric layer with a high dielectric constant. The method improves the qualities of the capacitor dielectric layer, for example the pinhole defects in the silicon nitride layer is unmatched. In the first preferred embodiment, the steps are as follows: at first, a semiconductor substrate having a DRAM transistor thereon and a bottom plate of the DRAM capacitor formed of polysilicon is prepared. Before loading the LPCVD chamber, a native oxide layer on the semiconductor substrate is removed using dilute HF solution. Thereafter, a first ammonium treatment is performed so as to form a first oxynitride layer. Subsequently, a first silicon nitride layer formed on the first oxynitride layer is followed. After a first HTO layer formed on the first silicon nitride layer, a second ammonium treatment is done so as to transform the first HTO layer into a second oxynitride layer. A second silicon nitride layer is then formed on the second oxynitride layer. A second HTO layer formed on the second silicon nitride layer is followed. Thereafter, a third ammonium treatment is performed so as to transform the second HTO layer into a third oxynitride layer. Finally, forming a polysilicon layer on the third oxynitride layer is done. The polysilicon layer is then patterned to be a top plate of the DRAM capacitor.
The second preferred embodiment provides the processes similar to the first preferred embodiment before depositing a third silicon nitride layer. However, the processing temperatures allowed are higher than those of operating in the first preferred embodiment. The semiconductor substrate is then transferred into a PECVD chamber to form a third silicon nitride layer on the second silicon nitride layer. An oxide layer formed on the third silicon nitride layer is followed. Subsequently, a third ammonium treatment is done so as to transform the oxide layer into a third oxynitride layer. Finally, as before, a polysilicon layer is formed and patterned on the third oxynitride layer for serving as the top plate of the DRAM capacitor.


REFERENCES:
patent: 5250456 (1993-10-01), Bryant
patent: 5661056 (1997-08-01), Takeuchi
patent: 5714399 (1998-02-01), Hisatomi et al.
patent: 6020238 (2000-02-01), He et al.
Mori et al, “bootom-Oxide scaling for thin nitride/oxide interpoly dielectric in stacked-gate nonviolateile memory cells”vol39. No.2, pp283-291

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