Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-22
2001-04-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S666000, C438S672000, C438S678000, C438S687000
Reexamination Certificate
active
06211071
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for forming a layer of an electrically conductive material filling a plurality of spaced apart recesses formed in the surface of a substrate, wherein the exposed upper surface of the layer is substantially coplanar with non-recessed areas of the substrate surface. More particularly, the invention relates to a “back-end” metallization method of manufacturing high-speed integrated circuit semiconductor devices having sub-micron dimensioned design features and high conductivity interconnect features, which method enables complete filling of the recesses, facilitates subsequent planarization of the metallized surface by chemical-mechanical polishing (CMP), increases manufacturing throughput, and improves product quality.
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming metal films as part of metallization processing of particular utility in integrated circuit semiconductor device and circuit board manufacture, and is especially adapted for use in processing employing “damascene” (or “in-laid”) technology.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-sized (e.g., 0.18 &mgr;m and below), low resistance-capacitance (RC) time constant metallization patterns, particularly wherein the submicron-sized metallization features such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to microminiaturization.
Semiconductor devices of the type contemplated herein typically comprise a semiconductor wafer substrate, usually of doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced apart metallization layers are electrically connected by a vertically oriented conductive plug filling a via hole formed in the interlayer dielectric separating the layers, while another conductive plug filling a contact area hole establishes electrical contact with an active region, such as a source/drain region, formed in or on the semiconductor substrate. Conductive lines formed in groove or trench-like openings in overlying dielectric layers extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type fabricated according to current technology may comprise five or more layers of such metallization in order to satisfy device geometry and miniaturization requirements.
Electrically conductive films or layers of the type contemplated herein for use in e.g., “back-end” semiconductor manufacturing technology as required for fabrication of devices as above described typically comprise a metal such as titanium, tantalum, tungsten, aluminum, chromium, nickel, cobalt, silver, gold, copper, and their alloys. In use, each of the recited metals presents advantages as well as drawbacks. For example, aluminum (Al) is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, in addition to being difficult to deposit by lower cost, lower temperature, more rapid “wet” technology such as electrodeposition, step coverage with Al is poor when the metallization features are scaled down to submicron size, resulting in decreased reliability of interconnections, high current densities at certain locations, and increased electromigration. In addition, low dielectric constant materials, e.g., polyamides, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with Al.
The use of via plugs filled with tungsten (W) may alleviate several problems associated with Al. However, most W-based processes are complex and expensive. In addition, the high resistivity of W may cause Joule heating which can undesirably enhance electromigration of Al in adjacent wiring. Moreover, W plugs are susceptible to void formation and high contact resistance at the interface with the Al wiring layer.
Copper (Cu) and Cu-based alloys are particularly attractive for use in large-scale integration (LSI), very large-scale integration (VLSI), and ultra large-scale integration (ULSI) devices requiring multilevel metallization systems for “back-end” processing of the semiconductor wafers on which the devices are based. Cu and Cu-based metallization systems have very low resistivities, i.e., significantly lower than that of W and even lower than those of previously preferred systems utilizing Al and its alloys, as well as significantly higher resistance to electromigration. Moreover, Cu and its alloys enjoy a considerable cost advantage over a number of the above-enumerated metals, notably silver and gold. Also, in contrast to Al and the refractory-type metals, Cu and its alloys can be readily deposited at low temperatures in good quality, bright layer form by well-known electroplating techniques, at deposition rates fully compatible with the requirements of device manufacturing throughput.
In addition to convenient, relatively low cost, low temperature, high throughput “wet” deposition by electroplating, Cu and its alloys are readily amenable to low cost, high throughput electroless deposition of high quality films for efficiently filling recesses such as vias, contact areas, and grooves and trenches forming interconnection routing. Such electroless plating generally involves the controlled autocatalytic deposition of a continuous film of Cu or an alloy thereof on a catalytic surface by the interaction of at least a Cu-containing salt and a chemical reducing agent contained in a suitable solution, whereas electroplating comprises employing electrons supplied to an electrode from an external source (i.e., a power supply) for reducing copper ions in solution and depositing reduced metal atoms on the surface thereof. In either case, a nucleation/seed layer is required for catalysis and/or deposition on the types of substrates contemplated for use herein. Finally, while electroplating requires a continuous nucleation/seed layer, very thin and discontinuous islands of a catalytic metal may be employed with electroless plating.
As indicated above, a commonly employed method for forming “in-laid” metallization patterns such as are required for “back-end” metallization processing of semiconductor wafers employs “damascene” type technology. Generally, in such damascene technology, a recess (i.e., an opening) for forming, e.g., a via hole in an inter-layer dielectric for electrically connecting vertically separated metallization layers, is created in the inter-layer dielectric by conventional photolithographic and etching techniques, and filled with a metal plug, typically of W. Any excess conductive material (i.e., W) on the surface of the inter-layer dielectric is then removed by, e.g., CMP, wherein a moving pad is biased against the surface to be polished, with the interposition of a slurry containing abrasive particles (and other ingredients) therebetween.
A variant of the above-described technique, termed “dual damascene” processing, involves the formation of an opening comprising a lower contact or via hole section in communication with an upper groove or trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Referring now to
FIG. 1
, schematically shown therein in simplified cross-sectional view is a conventional damascene processing sequence employing relatively low cost, high manufacturing throughput electroplating and CMP techniques for forming recessed “back-end” metallization patterns (illustratively of Cu-based metallurgy but not limited thereto) in a semicond
Avanzino Steven C.
Lukanc Todd P.
Wang Fei
Advanced Micro Devices , Inc.
Gurley Lynne A.
Niebling John F.
LandOfFree
Optimized trench/via profile for damascene filling does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Optimized trench/via profile for damascene filling, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimized trench/via profile for damascene filling will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2533860