Split gate flash memory cell with self-aligned process

Details Split gate flash memory cell with self-aligned process Split gate flash memory cell with self-aligned process

1998-11-17

2001-01-16

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C438S264000, C438S283000, C438S594000, C438S439000

Reexamination Certificate

active

06174771

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an improved method for fabricating split gate flash memories. More specifically, the present invention relates to a self-aligned process for making split-gate flash memory cells which eliminates the misalignment problem that can often occur between the floating gate (FG) and the field oxide (FOX), and/or the misalignment problem between the floating gate and the control gate (CG). The method disclosed in the present invention allows high-quality flash memory cells to be further scaled down in their cell dimension without incurring large capital investment or substantially increasing the manufacturing cost. With the split gate flash memory cells of the present invention, the cell programming is achieved through source coupling, as opposed to the conventional gate coupling, and, therefore, the zero overlap of floating gate on the field oxide does not degrade the programming efficiency.
BACKGROUND OF THE INVENTION
Flash memories are high-density nonvolatile semiconductor memories offering fast access times. Compared to other nonvolatile semiconductor memories such as conventional EPROMs or EEPROMs, flash memories are most suitable for applications wherein there are expected frequent write and read operations. Because of its light weight compared to magnetic memories such as hard disk or floppy disk memories, flash memory has a tremendous potential in the consumer electronics market. With the rapid growth of digital cameras and the desire for light-weight notebook PCs, the demand for even higher density flash memories is ever increasing.
U.S. Pat. Nos. 5,029,130, 5,045,488 5,067,108, and 5,202,850, the contents thereof are incorporated herein by reference, disclose a method of making an electrically programmable and erasable memory device having a re-crystallized floating gate. In the method disclosed in these patents, a substrate is first defined and a first layer of dielectric material is grown over the substrate. A layer of polysilicon or amorphous silicon is then deposited over the first layer. The silicon layer is covered with a protective material and is annealed to form re-crystallized silicon. A portion of the protective material is removed to define a floating gate region. A masking oxide is grown on the floating gate region, and the remainder of the protective material and the re-crystallized silicon thereunder is removed. A second layer of dielectric material is formed over the floating gate and over the substrate, immediately adjacent to the floating gate. Finally, a control gate is patterned and formed and source and drain regions are defined in the substrate.
FIG. 1A
shows a top view cell layout of a flash memory according to one of the prior art references mentioned above, and
FIGS. 1B and 1C
are illustrative cross-sectional views of the same flash memory cell along lines B-B′ and C-C′, respectively. The flash memory cell contains a semiconductor substrate
1
, which typically is a P-type silicon substrate with a doping level ranging from 5 to ohm-cm. Within the substrate
1
, there are drain region
2
, typically an N-doped silicon, a source region
3
, also an N-doped silicon, and a channel region
4
between the drain region
2
and the source region
3
. A tunnel oxide layer
5
is disposed over the channel region and the source and drain regions. Disposed over the tunnel oxide layer are one or more floating gates (poly-1), which, as shown in
FIG. 1C
, are positioned over a portion of the drain region
2
and over a portion of the channel region
4
. An insulating layer
6
, which can be silicon dioxide, silicon nitride, or silicon oxynitride, is disposed covering the floating gate. A control gate is then disposed which covers a portion of the floating gate and a portion of the channel region. During an erase operation, a ground potential is applied to the drain and the source regions, and a high positive voltage is applied to the control gate. The high positive voltage at the control gate causes charges, if any, on the floating gate to be injected through the so-called Fowler-Nordheim tunneling mechanism to tunnel through the insulating layer
6
to the control gate, allowing the floating gate to be discharged.
During programming or write operations, a ground potential is applied to the source region, a positive charge slightly exceeding the threshold voltage of the control gate region is applied to the control gate, and a high positive voltage is applied to the drain region. Under this condition, electrons will be generated by the source region which will flow from the source region towards the drain region through a relatively weakly inverted channel region. These electrons will see a large potential drop across the surface region defined by the gap of sidewall. Some of the electrons will become heated and be injected through the insulating layer into the floating gate, causing the floating gate to be charged. After the power is turned off, the insulating layer surrounding the floating gate prevents the escape of the charges that are stored in the floating gate.
However, several shortcomings in the above described flash memory structure have been recognized by the inventor of the present invention. Some of the more significant shortcomings include: (1) the existence of corner rounding of the field oxide pattern due to bird beak encroachment; (2) the existing of corner rounding of the poly-1 (floating gate) pattern due to limits in the current photolithography technology; (3) misalignment between the floating gate pattern and the field oxide pattern; (4) misalignment between the poly-1 (floating gate) pattern and the poly-2 (control gate) pattern; and (5) non-zero floating gate overlap with respect to the field oxide layer.
The frequent misalignment problem between the float gate pattern and the field oxide pattern becomes a bottleneck problem for the further scaling down of the flash memory cell. The misalignment between the poly-1 (floating gate) pattern and the poly-2 (control gate) pattern also causes different control gate length between two mirror cells. The two different control gate lengths (more specifically the peripheral lengths of the adjacent control gates) are shown as L
1
and L
2
, respectively, in FIG.
1
C. The problem of non-zero floating gate overlap with respect to the field oxide layer causes a reduction in the source coupling efficiency as well as other limitations in the cell scaling.
In light of the increasing importance of flash memory in the consumer electronics market, it is essential that substantial research and development efforts be devoted in this area so as to further improve the performance and quality of flash memory cells, and to allow the cell dimensions to be further reduced.
SUMMARY OF THE INVENTION
The primary object of the present invention is to develop an improved method for fabricating flash memory cells. More specifically, the primary object of the present invention is to develop an improved method for fabricating flash memory cells which eliminate many of the corner round-off and misalignment problems that have been experienced using the prior art methods.
Currently, the flash memory cells fabricated from existing methods have shown the following shortcomings:
(1) The existence of corner rounding of the filed oxide pattern due to bird beak encroachment.
(2) The existence of corner rounding of the poly-1 (floating gate) pattern due to limitations in the resolution of current photolithography technology.
(3) Misalignment between the floating gate pattern and the field oxide pattern. This problem has become a bottle-neck problem in attempts to achieve further down-scaling of flash memory cells utilizing the conventional photolithography technology.
(4) Misalignment between the poly-1 (floating gate) pattern and the poly-2 (control gate) pattern. This causes different control gate length immediately above the tunnel oxide layer.
(5) Non-zero floating gate overlap with respect to the field oxide layer. This causes reductions in the source coupling

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