Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-06
2001-07-31
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S282000
Reexamination Certificate
active
06268629
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which an FET (field effect transistor) with a MIS (Metal/Insulator/Semiconductor) structure is formed in an element region defined by trench isolation.
In recent years, as element isolation for a semiconductor integrated circuit, not the conventional element isolation using selective oxidation but so-called trench isolation wherein a trench is formed in a semiconductor substrate and an insulating film is buried in the trench to form an element isolation region is used. In this trench isolation, the bird's beak that is a problem in selective oxidation (LOCOS) is small, and the breakdown voltage can be kept satisfactory even when the element isolation width is small. Hence, the degree of integration can be increased.
However, in a MISFET formed by the conventional trench isolation process, the threshold voltage of side portions on both sides in the channel width direction undesirably becomes low. This is because when the surface layer is cleaned and exposed in the previous step of forming a gate insulating film on the surface of the semiconductor layer, the gate electrode is readily partially formed at a level lower than the interface between the semiconductor substrate and the gate insulating film.
FIG. 15A
is a sectional view showing the structure of a conventional MISFET. Referring to
FIG. 15A
, the MISFET has a semiconductor substrate
10
, element isolation trench
11
formed around an element region, insulating film
14
formed on the inner wall of the trench
11
, insulating film
15
buried in the trench
11
, impurity-implanted region
17
, gate insulating film
18
, and gate electrode
19
. Although not illustrated, source and drain regions are formed on the major surface of the substrate
10
on both sides of the channel region underneath the gate electrode
19
.
The major surface of the element region is almost flat. However, the end portions near the periphery of the trench (on both sides in the channel width direction) have tilt surfaces which are inevitably formed due to the manufacturing process. More specifically, to form the trench
11
, a buffer layer and etching stopper film are deposited on the substrate
10
. After a pattern is formed on these layers, a trench having a depth of 0.1 to 2 &mgr;m is formed in the substrate
10
. Next, the substrate
10
is annealed in an oxygen atmosphere to form the silicon oxide film
14
having a thickness of 5 to 100 nm in the trench
11
. During formation of this oxide film
14
, oxidation of the silicon substrate
10
progresses from the surface of the sides due to oxidation species such as oxygen or H
2
O entering the buffer layer. For this reason, the buffer layer becomes thicker at the trench side wall than at the flat portion to form a bird's beak, and a tilt surface due to the bird's beak is formed on the upper surface of the side portions of the element region.
Referring to
FIG. 15A
, a dotted line
20
represents the lower end of the channel depletion layer when the threshold voltage is applied to the gate electrode. La and Lb represent vertical distances (depths) from the interface between the gate insulating film
18
and the substrate
10
to the depletion layer end, which are measured in the vertical direction with respect to the major surface of the substrate. La is the depth at the flat substrate portion (main portion), and Lb is the depth at the tilt substrate portion (side portion) along the periphery of the trench. In the conventional process of implanting channel ions to a portion near the interface, when the bird's beak at the edge of the buffer layer is small, a channel ion profile is formed to a predetermined depth from the interface between the gate insulating film
18
and the substrate
10
.
Prior art
1
will be described next in detail in which the threshold voltage lowers in the arrangement shown in FIG.
15
A.
FIG. 15B
is an enlarged view of a side portion Sc in FIG.
15
A. Assume that the gate insulating film
18
has a uniform film thickness at the flat substrate portion and at the side portion along the periphery of the trench, or the gate insulating film
18
becomes thin at the side portion. In this case, as shown in
FIG. 15B
, the side portion of the substrate
10
is surrounded by the gate electrode
19
via the gate insulating film
18
at the upper and side surface portions. For this reason, the electric field from the electrode
19
concentrates in the side portion rather than in the main portion. When the gate insulating film
18
is thin at the side portion, field concentration is more noticeable.
In the conventional structure shown in
FIG. 15B
in which the distances La and Lb are almost equal, the substrate
10
is depleted from the side surface at the side portion due to the electric field from the side surface. For this reason, charge share of depletion layer charges from the semiconductor substrate surface decreases in correspondence with the depletion layer. The threshold voltage of the MISFET at the side portion becomes lower than that of the MISFET at the main portion, resulting in a parasitic side transistor. A line PL in
FIG. 15B
indicates the position of the peak of the dopant concentration in the channel region.
FIG. 16A
shows prior art
2
in which the threshold voltage is prevented from becoming lower even when a gate electrode
19
is partially formed at a level lower than the upper surface of a semiconductor substrate
10
. This structure has been discussed in, e.g., Tai-Su Park, Yu Gyun Shin, Han Sin Lee, Moon Han Park, Sang Dong, Kwon, Ho Kyu Kang, Young Bum Koh, and Moon Yong Lee, International Electron Devices Meeting Technical Digest, 1996, pp. 747-750, FIG.
11
A. The film structure other than the channel profile structure is known.
In prior art
2
, the tilt surface of the side portion of the element region is wider. An insulating film
14
also remains on this tilt surface. This structure is preferable not to form any parasitic transistor having a low threshold voltage at the side portion. In this case, at a portion where the insulating film
14
is formed on the tilt surface, the channel impurity having its maximal concentration value near the surface stays in the insulating film
14
without entering the substrate
10
. Hence, the concentration on the surface is lower at the side portion of the element region than at the main portion.
FIGS. 16B and 16C
are enlarged views of a side portion Sc between a gate electrode
19
and the substrate
10
. A dotted line
20
indicates the channel depletion layer end. La and Lb represent depths from the interface between a gate insulating film
18
and the substrate
10
, which are measured in the vertical direction with respect to the major surface of the substrate. La is the depth at the flat semiconductor substrate portion (main portion), and Lb is the depth at the side along the periphery of the trench. A line PL in
FIGS. 16B and 16C
indicates the position of the peak of the dopant concentration in the channel region.
In prior art
2
, the insulating film
14
is formed in advance on the tilt surface of the side portion. Referring to
FIG. 16B
, at the side portion of the semiconductor substrate along the periphery of the trench, which is covered with the insulating film
14
, the insulating film sandwiched by the gate electrode
19
and semiconductor substrate
10
can be made thicker than the gate insulating film
18
. More specifically, the insulating film
14
at the side portion is formed thicker than the gate insulating film
18
at the main portion such that the insulating film
14
is left at the side portion. In this state, the gate insulating film
18
is formed. With this process, the insulating film
14
thicker than the gate insulating film
18
is formed at the side portion between the gate electrode
19
and the substrate
10
. In the region covered with the insulating film
14
, a parasitic transistor with a low threshold voltage is hard to form.
On the other hand, at the side port
Chaudhuri Olik
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Pizarro-Crespo Marcos D.
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