Method of forming a dram crown capacitor

Details Method of forming a dram crown capacitor Method of forming a dram crown capacitor

1999-09-14

2001-08-07

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S240000, C438S256000, C438S396000, C438S399000

Reexamination Certificate

active

06271083

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention generally relates to a method of forming a DRAM crown capacitor, and more precisely to a method of forming a DRAM crown capacitor with BST (barium strontium titanate) as the dielectric layer of the capacitor.
2. Background of the Related Art
To shrink the device size is one of the aspects in the semiconducting industry. Since the sizes of the memory cells are scaled-down, the capacitance of the memory-capacitor must be refreshed frequently to maintain the storage the data of the memory cells. Otherwise, the capacitance of the memory-capacitor should be upgraded while the packaging density is increased. New materials or new structures of memory-capacitor are needed for improvement of the semiconducting industry.
Prior arts for overcoming these problems have resulted in the development of the trench capacitor (referrong to example U.S. Pat. No. 5,374,580) and the stacked capacitor. The trench capacitor has well-known problem of “gated didoe leakage,” which is the leakage of current resulting in the trench capacitor failing to hold a charge. Reducing the thickness of the capacitor dielectric also can improve the capacitance of the capacitor, but this approach is limited because of yield and reliabilty problems.
High dielectric material BST (barium strontium titanate) is widely regards as the capacitor dielectric for 1G or 4 G DRAM. Prior arts using the BST to serve as the dielectric films of memory cells have been published. For example, one prior art is referred to U.S. Pat. No. 5,619,051 entitled of “Semiconductor Nonvolatile Memory Cell” has been reported by Nobuhiro Endo. In the patent the BST is used to act as second dielectric films. Further, S. R. Summerfeild et al. have disclosed using BST to serve as the dielectric layer of the semiconductor in U.S. Pat. No. 5,825,055 “Fabricating High-dielectric Constant Oxides on Semiconductors Using a GE Buffer Layer”.
However, forming the BST layer always needs in high temperature ambience. Referring to the U.S. Pat. No. 5,552,305 reported by R. J. Cava et al., the recipes of forming the BST are disclosed. Otherwise, the attempts to adapt the BST to silicon technology have been intensively carried out, there are few successful results reported because of integration problems. Further, the BST film usually requires high temperature deposition in oxygenic ambiance. Platium (Pt) is the most studied electrode material for BST capacitors due to its high oxidation resistance and low leakage current. But the disadvantages of Pt are that the adhesion on oxide is poor, the Pt is hard to be etched by dry etching. Further, it tempts to react with poly and the cost of formation is higher. Hence, a new structure is developed to solve these problems.
SUMMARY OF THE INVENTION
According to one aspect of the invention is to provide a method of forming a new structure of DRAM capacitor. Especially, it is to provide a method of forming a BST (barium strontium titanate) as the capacitor dielectric and using platinum (Pt) as the electrodes of DRAM capacitor.
The method of forming the DRAM capacitor comprises the following steps. First, a substrate is provided for forming capacitor on the substrate wherein the substrate has at least one transistor on it. Then, a silicon oxide layer is formed on the substrate. Then, a nitride layer is formed on the silicon oxide layer. After etching the nitride layer and the silicon oxide layer, a contact hole for forming plug is then formed on the substrate. Therefore, the source/drain of the transistor is exposed in the contact hole. Subsequently, a polysilicon is filled in the contact hole. Sucessively, the W-metal (selective tungsten metal) is deposited on the polysilicon for protecting the polysilicon from a platinum layer wherin the platinum layer is formed in the following step. Furthermore, the surface of the W-metal (selective tungsten metal) is exposed outside the nitride layer and is planed with the nitride layer. Then, an oxide layer is deposited on the nitride layer and W-metal (selective tungsten metal). The oxide layer is then patterned to form a trench wherein the trench is for use to form a crown capacitor; and further, the W-metal (selective tungsten metal) and partial nitride layer are exposed in the trench. Then, a barrier metal layer is formed on the trench, the oxide layer, the partial nitride layer and W-metal (selective tungsten metal). Next, the platinum layer is formed on the barrier metal layer. The barrier metal layer and platinum layer act as the bottom electrode of DRAM capacitor. Further, a photo resist is formed on the platinum layer for use to protect the bottom electrode layer. Using CMP technique the shape of the bottom electrode can be defined precisely. Subsequently, the photo resist is removed. Then, a dielectric layer is formed on the platinum layer and the oxide layer using BST material. After the dielectric layer is formed, another platinum layer is formed to serve as the top electrode layer on the dielectric layer. Finally, the DRAM capacitor in present invention is fabricated.


REFERENCES:
patent: 5374580 (1994-12-01), Baglee et al.
patent: 5552355 (1996-09-01), Cava et al.
patent: 5619051 (1997-04-01), Endo
patent: 5668041 (1997-09-01), Okudaira et al.
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