Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-30
2001-05-08
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S279000
Reexamination Certificate
active
06228715
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The entire disclosure of Japanese Patent Application No. Hei 10-187707 filed on Jul. 2, 1998 including specification, claims, drawings and summary is incorporated herein by reference in its entirety.
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory device and a method of manufacturing thereof, more specifically to a technology so called “Self Aligned Source” (hereinafter referred to as SAS technology) for higher integration of semiconductor memory devices.
2. Description of the Related Art
The SAS technology is known as a technique for realizing higher integration of nonvolatile semiconductor devices such as flash erasable programmable ROMs (hereinafter referred to as EPROM) and so on. A manufacturing method of memory arrays using the SAS technology will be described with reference to
FIGS. 24A through 25B
. As shown in
FIG. 24A
, field oxidation layers
4
for device separation are formed on a semiconductor substrate
2
so as to extend in a direction of X as longitudinal direction in stripe shape.
Next, stacked gates
6
(extending in a direction of Y as longitudinal direction in stripe shape) are formed at right angles to the field oxidation layers
4
as shown in FIG.
24
B. Each of the stacked gates
6
has a structure that includes a gate oxidation layer
8
, a floating gate
10
, a layer
12
composed of an oxide film, a nitride film, and another oxide film (hereinafter referred to as ONO layer), and a control gate
14
formed in that order on a channel region CH defined in a memory cell (represented by memory cell MC shown in FIG.
25
B).
Although, the gate oxidation layer
8
, the floating gate
10
, and the ONO layer
12
in the stacked gate
6
, are formed so as to electrically isolate from the ones formed in another memory cell located adjacently, the control gate
14
is formed so as to electrically be connected to the memory cell with the one in the adjacent memory cell which forms the same column (a plurality of the memory cells located in a direction of Y, see FIG.
24
B).
Then, a drain D and a low density source LS are formed under self-aligning manner using both the stacked gate
6
and the field oxidation layer
4
. The drain D and the low density source LS are commonly used for two memory cells located adjacently, both form the same row (located in the direction of X).
Next, a resist layer
16
is formed so as to cover the drain D as depicted in
FIG. 25A
, and anisotropic etching having a high selectivity to silicon oxide is carried out by using both the resist layer
16
and the stacked gate
6
as a mask. The etching is generally referred to as SAS etching. A part of the field oxidation layer
4
lying between the adjacent memory cells which form the same column (in the direction of Y) is selectively removed by carrying out the SAS etching.
Highly concentrated arsenic (As) is ionically implanted to all over the substrate under the condition described above. In this way, the highly concentrated arsenic is implanted into both source formation regions commonly used for the adjacent memory cells which form the same row and regions connecting the source formation regions located in the column direction, in other words the regions are regions where the field oxidation layer
4
was removed therefrom as a result of the SAS etching.
Thereafter, a diffusion source wiring
15
connecting high density sources HS in the direction of Y is formed by carrying out thermal treatment to the substrate as depicted in FIG.
25
B. In this way, the diffusion source wiring
15
can be formed under self-aligning manner using the stacked gates
6
. These are the procedures carried out in SAS technology. Integration of semiconductor memory devices can be increased by using the SAS technology.
The SAS technology described above, however, has the following problems to be solved. Both an edge (a side) of the gate oxidation layer
8
and the surface of a source region S are unexpectedly etched in a certain extent during the SAS etching as shown in
FIG. 26
which is illustrated under enlarged manner.
Unstable shape of the gate edge
19
which plays important roles for writing/erasing data into/from the memory cell MC, may arise undesirably when the problems exist as they are. In other words, voltages required for the data writing/erasing into/from the memory cell MC and duration for applying the voltages, possibly be varied in a large extent.
In order to solve these problems, an improved SAS technology shown in
FIGS. 27A through 28B
was proposed (see Japanese laid open publication No. Hei 7-312395). Both
FIGS. 27A and 28A
correspond to a section
27
A shown in
FIG. 25A
, and these figures are concerned with the improved SAS technology. Both
FIGS. 27B and 28B
correspond to another section
27
B shown in
FIG. 25A
, and these figures are also concerned with the improved SAS technology.
In the improved SAS technology, a low density source LS, a high density source HS, and a drain D are formed after forming thereof under self-aligning manner using the stacked gate
6
. Thereafter, side walls
18
made of silicon oxides are formed on both sides of the stacked gate
6
before carrying out the SAS etching as shown in
FIGS. 27A and 27B
.
The side walls
18
are formed within the processes for manufacturing MOSFETs having Lightly Doped Drains (hereinafter referred to as LDD) which form peripheral circuits. In other words, the side walls
18
are formed by depositing silicon oxide by means of chemical vapor deposition (hereinafter referred to as CVD) or similar method, and then anisotropic etching is carried out thereto (carrying out etch-back processes). As a result, the side walls
18
becomes layers having a considerable thickness in the direction of X.
Thereafter, the SAS etching is carried out as shown in
FIGS. 28A and 28B
. The vicinity of the gate edge
19
is protected with the side walls
18
until completion of the SAS etching as shown in
FIG. 28B
even when the side walls
18
are etched during the SAS etching.
Then, highly concentrated arsenic (As) is ionically implanted to all over the substrate by using the resist layer
16
, the stacked gate
6
and the remained side walls
18
as a mask, and then thermal treatment is carried out to the substrate. In this way, a diffusion source wiring
15
connecting high density sources HS in the direction of Y, is formed as depicted in
FIG. 29
which shows a plan view of the vicinity thereof.
The improved SAS technology, however, has the following drawbacks to be resolved. Although, the gate edge
19
shown in
FIG. 28B
is protected from the SAS etching by employing the improved SAS technology, some portions of the diffusion source wiring
15
are undesirably narrowed in their width (to a width W
1
) as shown in FIG.
29
.
The regions where ions of arsenic are implanted thereinto, are narrowed for a width equivalent to twice as much (approximately 3,000 to 4,000 angstroms) as the width of the side wall
18
thus remained (typically 1,500 to 2,000 angstroms) because the remained side walls
18
are used as a mask against the ion implantation of the highly concentrated arsenic.
In this way, electric resistance of the diffusion source wiring
15
is unexpectedly increased for the reason of the narrowed portions. Therefore, unstable operations may be observed when the semiconductor memory device is applied especially to memories which require a large amount of source current during the data storage. This is because source voltages among memory elements vary in a large extent due to voltage drop caused thereamong. The drawbacks described above can be resolved when a width w
2
between the stacked gates
6
located adjacently is widen to a certain degree because the width w
1
is proportional to the width w
2
. The integration of the memories, on the other hand, is decreased by widening the width w
2
. The integration of the memories is decreased to about a half of that when the width w
2
is widen to approximately 3,000 through 4,000 angstroms in
Booth Richard
Merchant & Gould P.C.
Rohm & Co., Ltd.
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