Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-06-28
2001-09-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189070
Reexamination Certificate
active
06285601
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to buffers that are commonly used in integrated circuit devices to provide a location to place data until the data is retrieved or used by another portion of the integrated circuit device.
2. Description of the Related Art
Integrated circuit devices may be of many different types, including, for example, microprocessors, memory devices, specialized controllers, and communication devices of many different types. Frequently, integrated circuit devices of various types will be combined and interconnected by way of buses. Typically, data (including, for example, addresses, instructions and information) will be passed between the integrated circuit devices connected to the bus. For many well-known reasons, the different integrated circuit devices operate internally at different speeds from one another, and the integrated circuit devices may each be capable of transferring data to and from themselves at differing rates. To make up for these variations in transfer speed between a supplier of data and a consumer of data, a memory device known as a buffer may be used. A buffer provides a location to place data waiting to be consumed. A buffer may also be used to provide a location to collect some minimum amount of data before a consumer begins moving the grouped data to minimize the overhead of carrying the grouped data along a bus or other communication channel, for example.
Buffers are typically filled by a producer and emptied by a consumer. If the producer produces data that cannot be placed in the buffer, because the buffer is full, for example, then the data may be lost and the process damaged. Therefore, the usage model of a buffer is that a controller fills the buffer until the level of data in the buffer is such that the buffer should be emptied. This level is usually arbitrary within a certain range: large enough to be worth transferring the data over a channel that has certain overhead for any given transfer, yet small enough that the data should not overrun the buffer's maximum size. If the buffer transfer request threshold is set too small, then the buffer will be under-utilized. If the buffer transfer request threshold is set too high, the buffer will sometimes overflow, resulting in lost data, among other possible drawbacks. Typically, the buffer transfer request threshold is set as a compromise between a “too low” level and a “too high” level. For example, buffers used in many communications devices are set permanently and then forced to work in that compromised mode at all times. The buffer usage model changes when there are various levels of priority to the servicing of the buffer. Such multi-level priority buses and mechanisms exist, and communications with single buffer threshold levels are not the most efficient way to use a variable priority service mechanism.
To illustrate, consider a bus mechanism utilized to move data from a buffer in a device to memory or some other location closer to the consumer of the data. The bus, in attempting to maximize performance, is organized to carry large amounts of data at one time and to be fair to each of the bus devices or agents, allowing them each to participate on the bus with a transfer of data. If the bus mechanism handles all requests at the same priority level and empties the buffer between other long transfers on the bus, the bus will continue to be efficient. However, the maximum amount of time that may be taken by all other devices on the bus, before the buffer can again be serviced, might be quite long and exceed the ability of the buffer to hold its incoming data. If the buffer is sized large enough to support the maximum amount of time that other agents use the bus (known as latency) before it can be serviced in the worst case, the buffer is then much larger than the average size needed in the average transfer with average latency (between a request and the service). This situation leads to very large buffers that cost more than buffers that would be used in average situations without the latencies of the other bus devices. Such a buffer is shown in FIG.
1
.
FIG. 1
illustrates a buffer
10
that is sized to accommodate a level
13
of data that may accumulate before the system empties the buffer
10
under worst-cast conditions. Level
12
represents an empty buffer. Until the buffer
10
is filled to a minimum level
14
, not enough data is accumulated to efficiently transfer that data across the bus or other transport mechanism. The level
15
represents an amount of data accumulated after which the buffer
10
will be emptied by the system under the most favorable service conditions. The level
16
represents an amount of data that will accumulate before the buffer
10
is emptied, on average. Thus, the span
17
illustrates the buffer capacity that is “wasted” between the maximum possible capacity requirement and the minimum required capacity, and the span
18
illustrates the buffer capacity that is “wasted” on average, that is, the capacity between the maximum possible capacity requirement and the capacity needed on average.
Alternatively, a bus may have the ability to service a buffer at a higher priority level through various bus priority controls, arbitration controls or ordering mechanisms. In this situation, the buffer may fill until it is required to be emptied, at which time the bus mechanism will stop all of the transactions to complete the buffer transfer and empty the buffer. This higher level priority response has its own costs. Regardless of the mechanism used, the bus mechanism must interrupt or defer another transfer that was previously scheduled to occur or was already in progress, resulting in lowered bus efficiency.
The present invention is directed to a buffer and its associated control mechanism that solves, or at least reduces, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
A buffer control apparatus according to the present invention generally comprises a storage device that is adapted to store first and second buffer threshold values, and a circuit coupled to the storage device and coupled to receive an indication of a quantity of data in the buffer. The circuit is adapted to provide a first output signal when the quantity of data in the buffer is at least equal to the first buffer threshold value and a second output signal when the quantity of data in the buffer is at least equal to the second buffer threshold value. The storage device may comprise first and second storage devices, such as registers. The circuit may comprise a comparator or first and second comparators.
The method according to the present invention generally includes providing a first signal indicative of a level of data in the buffer, comparing a first threshold value to the first signal, generating a first output signal when the level of data in the buffer is at least equal to the first threshold value, comparing a second threshold value to the first signal, and generating a second output signal when the level of data in the buffer is at least equal to the second threshold value.
REFERENCES:
patent: 4707738 (1987-11-01), Ferre et al.
Advanced Micro Devices , Inc.
Nelms David
Tran M.
Williams Morgan & Amerson P.C.
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