Method for manufacturing gate terminal

Details Method for manufacturing gate terminal Method for manufacturing gate terminal

1998-02-24

2001-03-06

Bowers, Charles (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S429000, C438S430000, C438S424000, C438S585000, C438S637000, C438S639000, C438S738000

Reexamination Certificate

active

06197642

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 86115363, filed Oct. 18, 1997, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing of a semiconductor device. More particularly, the present invention relates to the method for manufacturing a gate terminal.
2. Description of Related Art
Metallic gate terminals are now extensively used in the fabrication of the gate of a metal oxide semiconductor (MOS) device. This is because the metallic gate terminal has a low resistance; moreover, no extra impurities implantation is necessary for increasing its electrical conductivity. Tungsten is one of the most commonly used materials for forming the gate terminal.
Generally, the metallic tungsten layer is deposited using plasma or laser-enhanced chemical vapor deposition method, or a physical sputtering method. However, during the process of depositing tungsten using plasma or laser-enhanced chemical vapor deposition method, the settling location of the metallic atoms being bombarded by the plasma or laser is difficult to control.
Furthermore, there will be some other impurities having enough energy to settle onto the gate terminal, thereby leading to a poor gate oxide layer and increasing the resistance of the gate terminal. Using a low pressure chemical vapor deposition method is able somehow to prevent the defects of poor gate oxide quality and increased resistance in plasma or laser-enhanced chemical vapor deposition method. However, a rather high temperature of greater than 350° C. are often necessary to deposit tungsten layer over the gate oxide layer. Hence, processing difficulties are increased.
FIGS. 1A through 1D
are cross-sectional views showing the progression of manufacturing steps in the fabrication of a conventional gate terminal. First, as shown in
FIG. 1A
, a substrate
10
is provided. Then, a shallow trench isolation structure
12
and a well (not shown) are formed in the substrate
10
.
Next, as shown in
FIG. 1B
, a gate oxide layer
14
is formed over the substrate
10
, for example, using a thermal oxidation method. Subsequently, a sputtering method is used to form a tungsten layer
16
over the gate oxide layer
14
. Then, the tungsten layer
16
and the gate oxide layer
14
are patterned to form a gate terminal. The tungsten layer
16
can be patterned, for example, by first coating a photoresist layer (not shown) over the tungsten layer
16
while exposing specific portions of the tungsten layer
16
. Next, a reactive ion etching (RIE) method is used to remove the exposed tungsten layer
16
, and then the gate oxide layer
14
is further etched until the substrate
10
is reached. Later, the photoresist layer is removed.
Next, as shown in
FIG. 1D
, subsequent processes are carried out. Ions of low concentration level are then implanted into the substrate on each side of the gate forming lightly doped source/drain regions
17
. Thereafter, an oxide layer is formed over the gate and the substrate
10
, for example, using a low pressure chemical vapor deposition method. Next, the oxide layer is anisotropically etched back to form spacers
18
on the sidewalls of the gate using a plasma etching-back method. Using the spacers
18
as masks, highly concentrated ions are then implanted into the substrate on the side of each spacer to form heavily doped source/drain regions
19
.
Since a rather high temperature of greater than 350° C. is necessary to deposit a tungsten layer over the gate oxide layer in order to form an electrode, semiconductor processing difficulties are increased.
Furthermore, since the etching process used in a conventional method of patterning the tungsten layer
16
to form a gate electrode is not easy to control, the correct gate dimensions are difficult to get.
In light of the foregoing, there is a need in the art for an improved method for forming a gate terminal.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to provide a method for manufacturing a gate terminal that is capable of eliminating the need for a high temperature deposition of tungsten over the gate oxide layer, and the difficulties in getting the correct gate dimensions in patterning the tungsten layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for manufacturing a gate terminal. The method comprises the steps of providing a substrate having an isolation structure and a well already formed thereon. An oxide layer is then formed over the substrate followed by patterning the oxide layer to form an opening serving as a gate region. Thereafter, a gate oxide layer is formed over the gate region, and then a crystalline silicon layer is formed over the gate oxide layer and over the sidewalls of the oxide layer. Subsequently, a chemical vapor deposition method, for example, using silane to reduce tungsten fluoride (WF
6
), is employed to deposit a layer of tungsten over the gate region. Next, a chemical-mechanical polishing method is used to polish the tungsten layer to a level almost the same as the oxide layer and forming a tungsten gate electrode. Finally, the oxide layer is removed.
After the removal of the oxide layer, further includes the steps of forming a lightly doped source/drain region in the substrate on each side of the tungsten layer. Then, spacers are formed on each sidewall of the metallic layer. Finally, a heavily doped source/drain region is formed in the substrate on each side of the spacers.
One aspect of this invention is the patterning of a gate region before the deposition of tungsten to form a gate terminal. This enables a proper control over the gate dimensions.
In another aspect, this invention overcomes the difficulties in controlling the etching operation in a conventional method of gate manufacture.
In yet another aspect, the formation of a thin crystalline silicon layer over the gate oxide layer in this invention is able to increase the bonding strength with a metallic layer. This thin crystalline Si can be consumpted during WCVD. Furthermore, a lower temperature can be used to form the gate terminal. Hence, a high quality gate terminal can be formed in addition to the ease of processing.
In a fourth aspect, the use of a silicon nitride layer as an etching stop layer for etching the oxide layer can prevent the over-exposure of the upper corner locations in shallow trench isolation. Thus, kink effect that may cause sub-threshold current and current leakage problems can be prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5489543 (1996-02-01), Hong
patent: 5534447 (1996-07-01), Hong
patent: 5538913 (1996-07-01), Hong
patent: 5658811 (1997-08-01), Kimura et al.
patent: 5899719 (1999-05-01), Hong
patent: 5918132 (1999-06-01), Qian et al.
patent: 5960270 (1999-09-01), Misra et al.
patent: 6004852 (1999-12-01), Yeh et al.
patent: 6008515 (1999-12-01), Hsia et al.
patent: 6015727 (2000-01-01), Wanlass
Wolf “Silicon Processing for the VLSI Era-vol. 1,” pp. 168-170 and 534, 1986.
Kimura et al “Short-channel-effect-supressed sub-0.1-micron grooved-gate MOSFET's with W gates,” IEEE Trans. Electr. Dev., vol. 42, No. 1 pp. 94-100, Jan. 1995.
Wong et al “Satpoly: A self-aligned tunsten on polysilicon process for CMOS VLSI applications,” IEEE Trans. Elect. Dev., vol. 36, No. 7, pp. 1355-1361, Jul. 1989.

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