Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-17
2001-07-03
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S303000, C438S592000, C438S595000, C438S655000, C438S656000, C438S721000
Reexamination Certificate
active
06255173
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, particularly to a method of forming a gate electrode for a MOSFET, and more particularly to a method of forming a gate electrode with a titanium polycide structure.
2. Description of the Related Art
In general, a gate electrode of a MOS transistor has been formed of a doped polysilicon layer. However, as high integration of semiconductor device, the line width of a gate electrode and other patterns becomes fine. Recently, the line width is reduced below 0.15 &mgr;m. Therefore, there are problems that it is difficult to apply the doped polysilicon layer to a gate electrode material in a high speed device, since the doped polysiliocn layer has a high resistivity. These problems are also growing more and more serious as the high integration of the semiconductor. To overcome these problems, a gate electrode with a titanium polycide structure in which a titanium silicide layer is formed on the polysilicon layer, is applied to a semiconductor device of IG DRAM or more.
Here, the titanium silicide layer is formed by two methods as follows.
A first method deposits a titanium (Ti) layer on a polysilicon layer and performs annealing, to react the Ti with Si of the polysilicon layer, thereby forming a titanium silicide (TiSi
2
) layer. A second method deposits a TiSi
x
layer of an amorphous phase on a polysilicon layer by physical vapor deposition (PVD) using a TiSi
x
sputtering target and performs annealing, thereby forming a TiSi
2
layer of a crystalline phase.
FIG. 1A
to
FIG. 1E
are cross sectional views describing a method of forming a gate electrode with a titanium polycide structure in which a titanium silicide layer is formed on the polysilicon layer according to the prior art using the second method.
Referring to
FIG. 1A
, a gate oxide layer
11
is grown on a semiconductor substrate
10
and a doped polysilicon layer
12
is deposited thereon. Referring to
FIG. 1B
, a TiSi
x
layer
13
of an amorphous phase is deposited on the polysilicon layer
12
by PVD using a TiSi
x
target.
Referring to
FIG. 1C
, rapid thermal process (RTP) is performed at a selected temperature for several seconds to transform the TiSi
x
layer
13
of the amorphous phase into a TiSi
2
layer
13
a
of a crystalline phase. Next, for performing subsequent process such as self-aligned contact (SAC), a mask nitride layer (or oxide layer) is deposited on the TiSi
2
layer
13
a.
Referring to
FIG. 1D
, the mask nitride layer
14
, the TiSi
2
layer
13
a
and the polysilicon layer
12
are etched to form a gate electrode.
Referring to
FIG. 1E
, for removing damage and polysilicon residues due to the etching process and recovering the reliability of the gate oxide layer
11
by forming a bird's beak, gate re-oxidation process is performed by well known method, so that an oxide layer
15
is formed on the side wall of the gate electrode.
However, when performing the gate re-oxidation process, the side wall portion of the TiSi
2
layer
13
a
is excessively oxidized, as shown in
FIG. 1E
, thereby increasing the resistivity of the gate electrode. Here, the oxidation of the TiSi
2
layer
13
a
is related to the mole ratio x of Si:Ti in the TiSi
x
sputtering target. More specifically, while in case the mole ratio x is below 2.1, the TiSi
2
layer is excessively oxidized, in case the mole ratio x is over 2.4, the TiSi
2
layer is moderately oxidized without any deformation. Namely, when silicon content of the TiSi
x
sputtering target is stoichiometrically excessive, the oxidation rate of the TiSi
2
layer
13
a
is equalized to that of the polysilicon layer
12
, so that the gate re-oxidation process can be performed.
However, the more the silicon content is high, the more particles increase, so that it is limited to use the TiSi
2
target having silicon content of 2.4 or more.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of forming a gate electrode with a titanium polycide structure capable of preventing abnormal oxidation of the gate electrode when performing gate re-oxidation process.
In the present invention, after forming a gate electrode having a stacked structure of a polysilicon layer and a titanium silicide layer, thermal-treating is performed under nitrogen atmosphere to form a TiN layer on the side wall of the titanium silicide layer, considering as the relative silicon content in the titanium silicide layer is high, abnormal oxidation decreases. At this time, a titanium silicide layer having deficient Ti is formed on the side wall of the titanium silicide layer adjacent to the TiN layer. Therefore, after removing the TiN layer, the side wall of the titanium silicide layer having excessive Si (or deficient Ti) is exposed. Thereafter, gate re-oxidation process is performed. At this time, abnormal oxidation of the titanium silicide layer is prevented by the titanium silicide layer having excessive silicon.
To accomplish this above objects, a method of forming a gate electrode with a titanium polycide structure according to the present invention, includes the steps of: forming a gate insulating layer and a polysilicon layer on a semiconductor substrate, in sequence; forming a titanium silicide layer on the polysilicon layer; sequentially etching the titanium silicide layer and the polysilicon layer to form a gate electrode; thermal-treating the resultant substrate under nitrogen atmosphere to form a TiN layer on the side wall of the titanium silicide layer and to form excessive silicon layer on the titanium silicide layer adjacent to the TiN layer; removing the TiN layer; and performing gate re-oxidation process.
Additional object, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
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S. Wolf, Silicon Processing for the VLSI Era, vol. 2, pp. 144-152, Lattice Press, Jan. 1990.
Hyundai Electronics Industries Co,. Ltd.
Keshavan Belur V
Selitto Behr & Kim
Smith Matthew
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