Trench isolation of field effect transistors

Details Trench isolation of field effect transistors Trench isolation of field effect transistors

1998-04-28

2001-08-14

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06274419

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to fabricating an integrated circuit, containing field effect transistors, with trench isolation and, more specifically, to fabricating the field effect transistors (FET) with trench isolation without parasitic transistors forming at the edges of the trenches, and the resulting integrated circuit with such isolating trenches.
BACKGROUND OF THE INVENTION
With higher levels of integrated circuits on semiconductor chips, such as silicon, and the need for faster transistors in these circuits, the FET transistor, with its gate separated from the silicon by a gate oxide and positioned between a source and drain in the silicon, must be fabricated to either minimize or eliminate any undesirable aspects, such as parasitic edge or corner transistors at the interface of the FET region and the trench at the crossover of the gate electrode to achieve FET transistors in integrated circuits with faster switching speed and without the potential of latchup.
Higher levels of integration requires increasing numbers of transistors isolated from each other in essentially the same amount of silicon real estate as lower levels of integration. Trench isolation, in contrast to recessed oxidation isolation, commonly know as LOCOS, is the formation of thin, vertical grooves in the silicon so that the amount of silicon real estate is minimized thereby leaving more silicon for the FETs and passive devices. Trenches normally are fabricated by anisotropically etching with a plasma gas(es) to which the silicon is selective to create substantially parallel walls or an U-shape groove deep in the silicon. If desired, V-shaped grooves can be formed by preferential wet etching of the (110) crystal plane of a {100} silicon wafer. Both of these trenches are filled with an insulating material, such as an oxide or nitride of silicon or an organic insulating material like polyimide. The walls of the etched silicon can be thermally oxidized prior to filling the trench, if so desired.
Although trench isolation saves silicon for more FETs and passive devices, this isolation technique produces parasitic transistors due to the source and drain impurities of the FET at the edges of the trench and the gate electrode crossing over and being recessed in the trench. These parasitic transistors are detrimental to the integrated circuit for at least two reasons. They increase the OFF current of the FETs, and they turn on at a lower voltage than the FETs and create a “subthreshold kink” in the current-voltage (I
D
-V
G
) characteristic curve. As the FETs are designed with smaller and smaller dimensions for higher levels of integration, the applied voltage to the FET is being lowered and the detrimental influence of the parasitic edge transistor on the operation of integrated circuit becomes even greater.
In addition, if a metal silicide is used as part of the gate electrode, junction leakage or breakdown may occur if the fabrication process allows the silicide to be in close proximity with the metallurgical junctions of the source and drain. Shorting also may occur if the metal silicide extends below metallurgical junction in the trench.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics.
Another object of the present invention is to provide a trench fabrication method in which the quality of the gate oxide can not be degraded during processing because no thinning of the gate oxide occurs in the trench edges or corners.
Still another object of the present invention is to provide a trench fabrication method which permits the use of metal silicide as part of the gate electrode without the possibility of junction leakage, breakdown and shorting.
A further object of the present invention is to provide a trench fabrication method of an integrated circuit is simpler to implement in manufacturing than known trench fabrication methods.
In accordance with the present invention, a semiconductor material, such as a silicon wafer, is formed with a layer capable of being conductive and function as a gate electrode, such as polysilicon after it is doped with an impurity, and with a gate insulating layer, such as an oxide, sandwiched between the silicon surface and the polysilicon. With an etch protective layer, which may also function as a polish protective layer, such as silicon nitride, covering the polysilicon surface, active areas are defined containing the FETs throughout the silicon wafer. Grooves are etched into the silicon, on the sides of the active areas, after etching through the protective layer, the gate electrode layer and the gate insulating layer into the silicon, and are filled with an insulating material to form trenches with their upper surface level with surface of the gate electrode layer after removal of the protective layer and planarization. The gate electrodes are defined and the layers between the defined gate electrode and the trenches are removed preferably sidewalls are formed on the sides of the gate electrodes and the exposed sides of the trenches. The fabrication of the FETs in the active areas are now completed using conventional processes techniques.
In accordance with another aspect of the present invention, the integrated circuit comprises an active area in which the upper surface of gate electrode of a FET in the active area is substantially in the same plane as the upper surfaces of isolating trenches on opposite sides of the active area. Preferably, insulating sidewalls are formed on the walls of the trenches prior to the formation of the source and drain of the FET and the gate electrode includes a metal silicide.


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