Semiconductor-oxide-semiconductor capacitor formed in...

Details Semiconductor-oxide-semiconductor capacitor formed in... Semiconductor-oxide-semiconductor capacitor formed in...

1998-11-05

2001-05-08

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000

Reexamination Certificate

active

06228696

ABSTRACT:

BACKGROUND
1. Field of the Invention
The invention relates generally to integrated circuits. The invention relates more specifically to the formation of a capacitor within an integrated circuit that has MOS transistors.
2. Description of the Related Art
It is often desirable to define capacitive elements within integrated circuits. A variety of different approaches have been developed. For example, two spaced-apart layers of metal interconnect may be used to form opposed plates of a capacitor. The insulator material between the two metal layers may be used as the dielectric. Such a metal-insulator-metal (MIM) capacitor can provide most of the desired characteristics of an ideal capacitor. In particular, such a MIM capacitor can have the ability to retain charge of either a positive or negative polarity without concern for which of the capacitor plates has the more positive or negative voltage.
When implemented in an integrated circuit, such a MIM capacitor has several drawbacks however. First, the thickness of the insulator between the metal layers tends to be relatively large. This may mean that relatively large amounts of metal area will be required for providing the MIM capacitor with a predefined, large amount of capacitance because capacitance is inversely proportional to dielectric thickness and directly proportional to plate area. Use of such large amounts of metal area may disadvantageously take away from the finite amount of metal area in the IC device. It is likely that the consumed metal area could have been otherwise put to better use for defining fine-pitch interconnect conductors of the integrated circuit. Metal interconnect tends to be a valuable resource that should not be squandered. Another drawback is that vias may be necessary for coupling terminals of the in-metal capacitor to other components in the substrate or first polysilicon layer of the IC device.
In an alternate approach, a capacitive element may be formed by shorting together the in-substrate drain and source regions of an NMOS or PMOS field effect transistor. These tied together transistor regions form part of an in-substrate first plate while the transistor's gate electrode defines an opposed second plate of a resulting, bipolar capacitor. The gate oxide defines the capacitor's dielectric. This shorted drain-source approach has the advantage of using the thin gate oxide of the IC device for providing greater values of capacitance. The shorted drain-source approach can advantageously avoid use of the scarce resources of metal layers if its connections are made entirely in the gate and substrate layers.
Unfortunately, the shorted drain-source capacitor has a shortcoming. The area of its in-the-substrate plate (the one formed by the tied-together source and drain) is typically intended to include the area of the transistor's conductive channel. Such a conductive channel is induced in the normally-depleted region below the gate and between the source and drain of the MOS transistor by appropriate gate-to-source biasing. And that is where the problem arises. If the shorted drain-source capacitor is expected to exhibit a maximum amount of capacitance—for the area consumed by the MOS transistor—then the gate-to-source voltage (V
GS
) of the transistor must be consistently maintained above threshold. This threshold (V
T
) is an inherent voltage of the MOS transistor which is needed to maintain the channel in the conductive or nondepleted state. However, if the voltage across the shorted drain-source capacitor modulates so as to extend into a region where the above-threshold condition (V
GS
>V
T
) is not maintained, the channel region depletes and the amount of capacitance changes substantially.
Design situations arise for which it is desirable to define within an IC device, a capacitor of essentially fixed capacitance where voltage across that capacitor is expected to swing through a voltage that constitutes threshold (V
T
) for at least one conductivity-type of transistor (NMOS or PMOS) in the same IC device. More specifically, design situations may arise for which the voltage across the desirably-fixed capacitance element is expected to swing at least between 0V and +V
DD
, where the latter range contains the threshold levels (V
TN
, V
TP
) of at least two different conductivity-types of transistors (NMOS and PMOS) in the same IC device. The traditional shorted source-drain NMOS or PMOS capacitor may not be useable in such situations because the gate-to-source voltage (V
GS
) will drop below threshold (V
GS
<V
T
) as capacitor voltage crosses dynamically through one or the other of the threshold values, V
TN
and V
TP
. The capacitance of the shorted source-drain MOS capacitor will then change significantly due to depletion of its channel.
The alternative use of a metal-insulator-metal (MIM) capacitor for such situations suffers the drawbacks noted above. As such, neither the MIM capacitor nor the shorted source-drain MOS capacitor provides an attractive solution.
SUMMARY OF THE INVENTION
An SOS capacitor in accordance with the invention overcomes the above problems. Such an SOS capacitor is defined by a sandwich of semiconductor-oxide-semiconductor layers where the opposed semiconductor layers both have an abundance of a same charge carrier (e.g., electrons).
In one embodiment, the first polysilicon layer of a CMOS integrated circuit defines an upper plate of the SOS capacitor, the gate oxide defines the insulator and an implanted well within the substrate defines the opposed plate. The implanted well has the same conductivity as that of the first polysilicon layer, meaning that they are either both of N type conductivity or both of P type conductivity.
Such an SOS structure may be efficiently fabricated at the same time and with most of the same process steps that are used for fabricating neighboring MOS transistors of the IC device. In other words, the SOS capacitor may utilize the same thin gate oxide for its dielectric as is used for forming the gate-to-channel isolation of neighboring MOS transistors. The SOS capacitor may utilize the same conductive gate layer (typically, the ‘poly-one’ layer) for its upper plate as is used for forming the gate electrodes of neighboring MOS transistors. Doping of the upper plate of the SOS capacitor may occur at the same time and with the same process used for doping the gate electrodes of neighboring MOS transistors.
Other aspects of the invention will become apparent from the below detailed description.


REFERENCES:
patent: 4922319 (1990-05-01), Fukushima
patent: 5523603 (1996-06-01), Fishbein et al.

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