Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-06
2001-04-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S299000, C438S290000, C438S305000, C438S407000, C438S528000
Reexamination Certificate
active
06221724
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method of fabricating an integrated circuit and more specifically to a method of fabricating an integrated circuit having punch-through suppression.
BACKGROUND OF THE INVENTION
In very large-scale integrated circuits (VLSI), and even more so in ultra large-scale integrated (ULSI) circuits, the channel length of transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) must be minimized. This allows a greater number of transistors to be fabricated on a single substrate and also provides for a faster transistor switching speed due to the shorter transit time of carriers moving between the source and the drain regions. One of the major difficulties with reducing the channel length is punch-through, in which the depletion layers from the source and drain regions contact one another, causing the potential barrier between the source and the drain to decrease. Punch-through results in significant leakage current, even when the transistor is in the off state.
The punch-through voltage (Vpt) of a device is defined as the drain-to-source voltage (Vds) at which the current from drain to source (Ids) reaches an unacceptable value with a gate-to-source voltage (Vgs) of zero. Punch-through must be suppressed in a device to the point where Vpt is larger than any possible Vds. One method for suppressing Vpt is to increase doping of the drain and source regions to decrease the depletion layer widths. Typically, this increased doping is used along with a threshold voltage adjust (Vt-adjust) implant. A Vt-adjust implant is a region of increased doping, e.g. boron in N-channel MOSFETs, phosphorous in P-channel MOSFETs. Other dopants for the Vt-adjust implant can include indium and boron difluoride (BF
2
). The Vt-adjust implant is typically implanted beneath the surface channel region to raise the dopant concentration beneath the surface channel region above the dopant concentration of the substrate. However, during the subsequent thermal annealing process, the dopant from this Vt-adjust implant may diffuse toward the surface and raise the dopant concentration in the channel, causing carrier mobility degradation due to increased impurity scattering.
Another method for suppressing Vpt is using “halo” implants. P-type dopants (in N-channel MOSFETs) are implanted under the lightly doped drain/source extensions (e.g., tip regions of the drain and source regions.) The implanted dopant raises the doping concentration only on the walls of the source and drain regions near the surface channel region. Thus, the channel length can be decreased without needing to use a substrate doped to a higher concentration. However, “halo” implants must be fabricated with great precision and may also result in an increase in the sidewall junction capacitance.
Accordingly, there is a need for an improved method of suppressing punch-through in an integrated circuit (IC). Further, there is a need for a method which allows for greater density of devices on the integrated circuit and improved efficiency of the IC. Even further still, there is a need for a punch-through suppression process which is easier to perform than prior punch-through suppression methods.
SUMMARY OF THE INVENTION
These and other limitations of the prior art are addressed by the present invention which is directed to a method of fabricating an integrated circuit having punch-through suppression between two regions of a device. According to one embodiment of the present invention, the device includes a channel region between the two regions. The method includes providing a semiconductor substrate; forming a gate on the substrate near the channel region; and implanting an implant material through the gate. The implant material accumulates below the channel region to provide punch-through suppression between the two regions of the device.
According to another feature of the present invention, the implant material includes inert ions and is also implanted through two regions of the device so that the inert ions form second and third accumulations below the surface of the two regions of the device.
According to another advantageous feature of the present invention, the substrate has a level of transient enhanced diffusion (TED) associated therewith and the inert ions operate to substantially neutralize the TED in the substrate.
According to yet another advantageous feature of the present invention, diffusion of dopant from the gate into the channel region of the substrate is suppressed by the implant material.
According to a second exemplary embodiment of the present invention, a method of fabricating an integrated circuit is provided, the integrated circuit having punch-through suppression between two regions of a device. In this second exemplary embodiment, the device includes a channel region between the two regions. The method includes providing a semiconductor substrate; implanting a punch-through dopant between the two regions of the device to form a punch-through dopant implant; forming a gate on the substrate near the channel region; and implanting an implant material through the gate so that the implant material accumulates beneath the channel region. This second exemplary embodiment provides suppression of punch-through between the two regions of the device and further suppresses diffusion of the punch-through dopant implant toward the channel region.
According to yet a third exemplary embodiment of the present invention, a method of fabricating an integrated circuit having electrical isolation between two regions of the integrated circuit is provided. The method includes providing a semiconductor substrate; forming a conductive structure on the substrate at a selected location; and implanting inert ions through the conductive structure and through the two regions of the device. The inert ions form a first accumulation below the selected location and second and third accumulations below the two regions of the device. The accumulations of inert ions provide electrical isolation of the two regions of the device.
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Pramanick Shekhar
Yu Bin
Advanced Micro Devices , Inc.
Foley & Lardner
Hack Jonathan
Niebling John F.
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