Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-04-21
2001-01-09
Monin, Jr., Donald L. (Department: 2814)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S706000, C438S734000, C148SDIG001, C216S052000
Reexamination Certificate
active
06171965
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of objects. More particularly, the present invention provides a technique for improving surface texture or surface characteristics of a film of material, e.g., silicon, silicon germanium, or others. The present invention can be applied to treating or smoothing a cleaved film from a layer transfer process for the manufacture of integrated circuits, for example. But it will be recognized that the invention has a wider range of applicability; it can also be applied to smoothing a film for other substrates such as multi-layered integrated circuit devices, three-dimensional packaging of integrated semiconductor devices, photonic devices, piezoelectronic devices, microelectromechanical systems (“MEMS”), sensors, actuators, solar cells, flat panel displays (e.g., LCD, AMLCD), doping semiconductor devices, biological and biomedical devices, and the like.
Integrated circuits are fabricated on chips of semiconductor material. These integrated circuits often contain thousands, or even millions, of transistors and other devices. In particular, it is desirable to put as many transistors as possible within a given area of semiconductor because more transistors typically provide greater functionality, and a smaller chip means more chips per wafer and lower costs. Some integrated circuits are fabricated on a slice or wafer, of single-crystal (monocrystalline) silicon, commonly termed a “bulk” silicon wafer. Devices on such “bulk” silicon wafer typically are isolated from each other. A variety of techniques have been proposed or used to isolate these devices from each other on the bulk silicon wafer, such as a local oxidation of silicon (“LOCOS”) process, trench isolation, and others. These techniques, however, are not free from limitations. For example, conventional isolation techniques consume a considerable amount of valuable wafer surface area on the chip, and often generate a non-planar surface as an artifact of the isolation process. Either or both of these considerations generally limit the degree of integration achievable in a given chip. Additionally, trench isolation often requires a process of reactive ion etching, which is extremely time consuming and can be difficult to achieve accurately.
An approach to achieving very-large scale integration (“VLSI”) or ultralarge scale integration (“ULSI”) is by using a semiconductor-on-insulator (“SOI”) wafer. An SOI wafer typically has a layer of silicon on top of a layer of an insulator material. A variety of techniques have been proposed or used for fabricating the SOI wafer. These techniques include, among others, growing a thin layer of silicon on a sapphire substrate, bonding a layer of silicon to an insulating substrate, and forming an insulating layer beneath a silicon layer in a bulk silicon wafer. In an SOI integrated circuit, essentially complete device isolation is often achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. An advantage SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer.
SOI offers other advantages over bulk silicon technologies as well. For example, SOI offers a simpler fabrication sequence compared to a bulk silicon wafer. Devices fabricated on an SOI wafer may also have better radiation resistance, less photo-induced current, and less cross-talk than devices fabricated on bulk silicon wafers. Many problems, however, that have already been solved regarding fabricating devices on bulk silicon wafers remain to be solved for fabricating devices on SOI wafers.
For example, SOI wafers generally must also be polished to remove any surface irregularities from the film of silicon overlying the insulating layer. Polishing generally includes, among others, chemical mechanical polishing, commonly termed CMP. CMP is generally time consuming and expensive, and can be difficult to perform cost efficiently to remove surface non-uniformities. That is, a CMP machine is expensive and requires large quantities of slurry mixture, which is also expensive. The slurry mixture can also be highly acidic or caustic. Accordingly, the slurry mixture can influence functionality and reliability of devices that are fabricated on the SOI wafer.
From the above, it is seen that an improved technique for manufacturing a substrate such as an SOI wafer is highly desirable.
SUMMARY OF THE INVENTION
According to the present invention, a technique for treating a film of material is provided. More particularly, the present invention provides a method for treating a cleaved surface and/or an implanted surface using a combination of thermal treatment and chemical reaction, which can form a substantially smooth film layer from the cleaved surface.
In a specific embodiment, the present invention provides a method for fabricating a substrate, e.g., silicon, silicon-on-insulator, silicon-on-silicon, and many others. The method includes providing a donor substrate comprising an upper surface. The method also includes introducing a plurality of particles (e.g., hydrogen, mixtures of hydrogen, helium/hydrogen, halogen/hydrogen) through the upper surface and into the donor substrate to a selected depth beneath the upper surface to define a thickness of material of the donor substrate defined from the upper surface to the selected depth. The plurality of particles are defined by a distribution along the selected depth, which ranges from a greater or maximum value to a reduced value. Next, energy is introduced to the donor substrate to initiate a cleaving action to free the thickness of material from the donor substrate to define a cleaved surface from the donor substrate. The cleaved surface has a surface roughness of a predetermined value, which is generally undesirable. The surface also has a portion of the distribution of the plurality of particles defined therein. The method also includes applying thermal treatment and an etchant (or deposition material or combination of etchant and deposition material) to the cleaved surface and the portion of the distribution of the plurality of particles to reduce the surface roughness from the predetermined value.
In an alternative embodiment, the present invention provides a semiconductor substrate. The substrate includes a cleaved surface, which is characterized by a predetermined surface roughness value. A distribution of hydrogen bearing particles are defined from the cleaved surface to a region underlying the cleaved film. The distribution of hydrogen particles assist in surface treatment of the cleaved film during subsequent heat treatment processes or the like. The substrate can be a semiconductor substrate as well as other types of substrates.
Numerous benefits are achieved by way of the present invention over preexisting techniques. For example, the present invention provides an efficient technique for forming a substantially uniform surface on an SOI wafer. Additionally, the substantially uniform surface is made by way of common hydrogen treatment and etching techniques, which can be found in conventional epitaxial tools. Furthermore, the present invention provides a novel uniform layer, which can be ready for the manufacture of integrated circuits. The present invention also relies upon standard fabrication gases such as HCl and hydrogen gas. In preferred embodiments, the present invention can improve bond interface integrity, improve crystal structure, and reduce defects in the substrate simultaneously during the process. Depending upon the embodiment, one or more of these benefits is present. These and other advantages or benefits are described throughout the present specification and are described more particularly below.
These and other embodiments of the present invention, as well as its advantages and features are described in more detail in conjunction with the text below and attached Figs.
REFERENCES:
paten
Kang Sien G.
Malik Igor J.
Monin, Jr. Donald L.
Rao S. H.
Silicon Genesis Corporation
Townsend & Townsend & Crew LLP
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