Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-30
2001-03-13
De Cady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06202182
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of testing of integrated circuit devices and, more particularly, to a method of testing field programmable gate arrays.
BACKGROUND OF THE INVENTION
A field programmable gate array (FPGA) is a type of integrated circuit consisting of an array of programmable logic blocks (PLBS) interconnected by a programmable routing network and programmable input/output cells. Programming of the logic blocks, the routing network and the input/output cells or boundary ports is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application
The present inventors have recently developed methods of built-in self-testing the array of PLBs in FPGAs at the device, board and system levels. These methods are set out in detail in U.S. Pat. No. 5,998,907 and U.S. Pat. No. 6,003,150. The fill disclosures in these patent applications are incorporated herein by reference.
In each of these prior methods, the reprogrammability of an FPGA is exploited so that the FPGA is configured exclusively with built-in self-test (BIST) logic during testing and subsequently reconfigured to its normal operating configuration. In this way, testability at every level is achieved without overhead. In other words, the BIST logic simply “disappears” when the FPGA is reconfigured for its normal system function. The only cost or additional hardware required for these testing methods is memory for storing the BIST configuration data required for testing and the normal operating configuration required for subsequently reconfiguring the FPGA. This additional memory, however, may be made a part of the test machine environment, e.g., automatic testing equipment, a central processing unit or a maintenance processor, thereby not involving FPGA resources.
In addition to testing the array of PLBs, complete FPGA testing further requires the testing of the programmable routing network. Heretofore, testing of the programmable routing network was accomplished utilizing externally applied test vectors. While the use of test vectors is effective in testing of the programmable routing network, these tests are applicable only for specific device-level manufacturing tests. Accordingly, a need is identified for testing the entire programmable routing network at the device, circuit board and system levels.
SUMMARY OF THE INVENTION
An important aspect of the present invention is to provide methods of built-in self-testing FPGAs including the PLBs and the programmable routing network to achieve a complete test at the device, board or system levels. These methods not only test the global routing network which interconnects the array of PLBs but also the local routing network which brings signals into and out of the individual PLBs within the array.
In accordance with the of the present invention, a method is provided for built-in self-testing a programmable routing network of a field programmable gate array (FPGA). The method may be broadly defined as configuring a first group of programmable logic blocks (PLBs) of the FPGA under test to include at least one test pattern generator (TPG) and at least one output response analyzer (ORA), and further configuring a subset of the programmable routing network into at least two groups of wires under test (WUTs). Upon initiation of the built-in self-test (BIST), the at least one TPG generates test patterns which propagate along the at least two groups of WUTs. The outputs of the at least two groups of WUTs are compared utilizing the at least one ORA which in turn generates a test result indication.
More specifically, the FPGA under test is configured in accordance with a BIST configuration retrieved from memory. Preferably, the BIST configured FPGA includes a first group of PLBs configured as at least one TPG for generating test patterns and at least one ORA for receiving and comparing the test patterns, and at least two groups of WUTs along which the test patterns are propagated.
In accordance with an important aspect of the present invention, and in order to achieve a complete BIST of the programmable routing network of the FPGA under test, the WUTs include wire segments interconnected by configurable interconnect points (CIPs) and a second group of PLBs. There are two basic types of CIPs, including cross-point and break-point, and each generally comprises a transmission gate controlled by a configuration memory bit. When incorporated into the WUTs, the second group of PLBs is specifically configured to allow the propagating test patterns to pass there through without alteration. Advantageously, this allows both the global routing network of the programmable routing network including the CIPs and the local routing structures leading to the PLBs to be tested.
In addition, the BIST configured FPGA may also include PLBs from the first group of PLBs configured to align one of the test patterns propagating along one of the at least two groups of WUTs prior to comparison by the ORA. More specifically, these PLBs are configured as swapper cells which map input test patterns to output test patterns. The need for alignment of one of the test patterns arises from the nature of the logic equations implemented in look-up tables (LUTs) of the ORA, the limitations on the inputs to the PLBs implementing the ORA, and the bus rotations in the WUTs.
Upon receipt of the test patterns, the at least one ORA generates a test result indication based on the outcome of the step of comparing outputs of the at least two groups of WUTs. A passing test result indication is generated if the corresponding test patterns are found to be the same upon reaching the at least one ORA. In the alternative, a failing test result indication is generated if the test patterns are not found to be the same. Such a failing test result indication may be caused by a fault in a wire segment, a CIP or a PLB of the at least two groups of WUTs.
One limitation of this type of comparison-based response analysis is the potential for equivalent faults in the outputs of the at least two groups of WUTs. Equivalent faults along the at least two groups of WUTs result in passing test result indications even though faults exist. Advantageously, to overcome this limitation the method of the present invention further includes the step of comparing the output or value transmitted along the first group of WUTs to the output or value transmitted along the second group of WUTs and the output or value transmitted along a third group of neighboring WUTs. This type of multiple testing substantially eliminates the potential for equivalent faults.
Additionally, in order to maintain a low number of reconfigurations of the FPGA under test and a short total testing time during the BIST, parallel testing is utilized. More specifically, the test result indications of several ORAs can be combined utilizing an iterative comparator. Alternatively, the test result indication generated by the at least one ORA can be routed directly to a boundary port of the FPGA under test. Advantageously, this provides information regarding the location of the fault in the FPGA under test, as opposed to the single pass/fail test result indication for the entire test.
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Abramovici Miron
Stroud Charles Eugene
Wijesuriya Sajitha S.
Cady Albert De
Chase Shelly A
King & Schickli PLLC
Lucent Technologies - Inc.
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