Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-05-05
2001-04-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S436000, C438S438000, C438S743000, C438S756000, C438S761000
Reexamination Certificate
active
06218268
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to fabrication processes suitable for manufacturing semiconductor integrated circuits (“ICs”), and more particularly to a two-step borophosphosilicate glass (“BPSG”) deposition process and related devices and apparatus.
The fabrication sequence of integrated circuits often includes several patterning processes. The patterning processes may define a layer of conductors, such as a patterned metal or polysilicon layer, or may define isolation structures, such as trenches. In many cases the trenches are filled with an insulating, or dielectric, material. This insulating material can serve several functions. The material serves to electrically isolate one region of the IC from another, and can also electrically passivate the surface of the trench. The material also typically provides a base for the next layer of the semiconductor to be built upon.
After patterning a substrate, that material is not flat. The topology of the pattern can interfere with or degrade subsequent wafer processing steps. It is often desirable to create a flat surface over the patterned material. Several methods have been developed to create such a flat, or “planarized”, surface. Examples include depositing a conformal layer of material of sufficient thickness and polishing the wafer to obtain a flat surface, depositing a conformal layer of material of sufficient thickness and etching the layer back to form a planarized surface, and forming a layer of relatively low-melting point material, such as BPSG, and then heating the wafer sufficiently to cause the BPSG to melt and flow as a liquid, resulting in a flat surface upon cooling. Each process has attributes that make that process desirable for a specific application.
Forming and then melting a layer of BPSG is a desirable layer-forming process for many reasons. The re-flow (melting) temperature of the BPSG is fairly low and the re-flow time is fairly brief, thus re-flow may be accomplished without significantly adding to the thermal budget of the device fabrication sequence. Additionally, BPSG may be doped to various doping concentrations to vary the re-flow characteristics. BPSG can flow to fill very fine features on the surface of a substrate, and can fill trenches of varying widths on a single substrate.
As semiconductor design has advanced, the feature size of the semiconductor devices has dramatically decreased. Many circuits now have features, such as traces or trenches less than a micron across. While the reduction in feature size has allowed higher device density, more chips per wafer, more complex circuits, lower operating power consumption, and lower cost, the smaller geometries have also given rise to new problems, or have resurrected problems that were once solved for larger geometries.
An example of the type of manufacturing challenge presented by sub-micron devices is the ability to completely fill a narrow trench in a void-free manner. To fill a trench with BPSG, a layer of BPSG is first deposited on the patterned substrate. The BPSG layer typically covers the field, as well as walls and bottom of the trench. If the trench is wide and shallow, it is relatively easy to completely fill the trench with BPSG. As the trench gets narrower and the aspect ratio (the ratio of the trench height to the trench width) increases, it becomes more likely that the opening of the trench will “pinch off”.
Pinching off a trench traps a void within the trench. Under certain conditions, the void will be filled during the re-flow process; however, as the trench becomes narrower, it becomes more likely that the void will not be filled during the reflow process. Such voids are undesirable as they can reduce the yield of good chips per wafer and the reliability of the devices. Therefore, it is desirable to be able to fill narrow gaps with BPSG in a void-free manner. It is also desirable that the process used to deposit and reflow BPSG be efficient, reliable, and result in a high yield of devices.
SUMMARY OF THE INVENTION
The present invention provides methods, apparatus, and devices related to doped silicon glass layers. In one embodiment, a two-step deposition process is used to efficiently form a BPSG layer with good gap-filling properties. The two-step deposition process is capable of filling trenches with openings of about 0.16 microns and aspect ratios of at least about 6:1 in a void-free manner, after re-flow of the deposited BPSG. A first portion of the BPSG layer is formed at a relatively high pressure and ozone-to-silicon deposition gas ratio, and a second portion of the BPSG layer is formed at a relatively low pressure and lower ozone-to-silicon deposition gas ratio.
In a further embodiment, the doping level of the first portion is higher than the doping level of the second portion. The highly doped first portion improves the re-flow properties, while the more lightly doped second portion enhances film stability. A bypass from the dopant source to the vacuum pump system allows dopant flow to be stabilized without flowing the dopant into the chamber. The dopant flow is switched from the vacuum pump system to the vacuum chamber by operation of a select valve. Use of the bypass allows a doped silicon glass layer to be formed without a dopant-deficient zone.
One device according to the present invention includes a re-flowed BPSG layer with a first portion having a wet etch rate ratio higher than the wet etch rate ratio of a second portion of the layer. Another embodiment of the invention is an intermediate IC structure that includes a doped silicon glass layer in contact with a silicon substrate, wherein the doped silicon glass layer does not have a dopant-deficient region adjoining the silicon substrate.
These and other embodiments of the present invention, as well as some of its advantages and features are described in more detail in conjunction with the text below and attached figures.
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Campana Francimar
Chandran Shankar
Galiano Maria
Xia Li-Qun
Yieh Ellie
Applied Materials Inc.
Malsawma Lex H.
Smith Matthew
Townsend and Townsend / and Crew LLP
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