Method of forming a trench capacitor

Details Method of forming a trench capacitor Method of forming a trench capacitor

1999-05-19

2001-08-07

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S386000

Reexamination Certificate

active

06271079

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a trench capacitor, and more particularly, to a method of forming a bottle shape trench capacitor with a sacrificial silicon nitride sidewall to increase the surface of the capacitor.
BACKGROUND OF THE INVENTION
In recent years, the development of the semiconductor memory device has become highly integrated and having high packing density. The area occupied by a capacitor of a DRAM storage cell has shrunk, thus decreasing the capacitance of the capacitor owing to its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise ratio in reading the memory cell and to reduce soft errors (due to alpha particle interference). Therefore, it is desirable to reduce the cell dimensions and yet obtain a high capacitance, which achieves both high cell integration and reliable operation.
The capacitor type that is most typically used in DRAM memory cells is planar capacitor, which is relatively simple to manufacture. For very small memory cells, planar capacitor becomes very difficult to use reliably. One approach for increasing the capacitance while maintaining the high integration of the memory cells is directed toward the shape of the capacitor electrodes. In this approach, the polysilicon layer implementing the capacitor electrodes may have protrusions, cavities, fins, etc., to increasing the surface area of the capacitor electrode, so that increases its capacitance while maintaining the small area occupied on the substrate surface.
When DRAM cells are scaled down while maintaining the cell capacitance, three-dimensional cell structures, such as trench capacitors, are widely developed. One of advantages of the trench capacitor cell is its large capacitance and planar topography. One of the prior arts in accordance with the trench capacitor can be seen “A 0.6 &mgr;m
2
256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), L. Nesbit et al., 1993, IEEE, IEDM 93-627”. A unique feature of this cell is a self-aligned buried strap that forms at the intersection of the storage trench and the junction of the array device. However, it is difficult to make deep trenches with a high aspect ratio for high density DRAMs.
An example of a conventional deep trench capacitor is depicted in
FIG. 1A
to FIG.
1
C. Referring to FIG. A, that shows a dielectric layer
102
is formed on a semiconductor substrate
101
, and a trench region
100
is formed by dry etching down. After the trench is etched, the N-type capacitor plate
103
is formed by outdiffusing arsenic or phosphoric from the lower portion of the trench. An oxidized nitride (NO) storage node dielectric
104
is formed in the storage trench, followed by the deposition and controlled recess of a first trench fill of n+ polysilicon
105
. See
FIG. 1B
, a collar oxide
106
is formed using conventional CVD process. The depth of buried strap is defined by a controlled etchback of a second polysilicon trench fill
107
and the removal of the exposed collar oxide. A third polysilicon film
108
, which contacts the silicon substrate along the exposed trench sidewall, is deposited and recessed below the silicon substrate surface.
When the dimension of DRAM is close to deep-submicron, a new method for manufacturing small capacitors is needed. A method to fabricate a trench capacitor on a smaller occupancy space with higher capacitance is needed.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an improved method of forming a trench capacitor.
The other object of the present invention is that to provide a method of forming a trench capacitor with a sacrificial silicon nitride sidewall, which protects a collar oxide been etched or doped.
A first silicon nitride layer a thick oxide layer are formed on a silicon substrate, then pattern said first silicon nitride layer and said thick oxide layer to form a deep trench region in said substrate. Subsequently, said thick oxide layer is removed away by wet etching. A TEOS oxide layer is then formed on said first silicon nitride layer and filled in said trench region by conventional process. The TEOS oxide layer is etched to a first level by dry etching, wherein a portion of the TEOS oxide layer is remained in the trench region and a portion of the silicon substrate exposed in the trench region. A thermally oxidation process is performed to form a collar oxide on the exposed silicon substrate. A second silicon nitride layer is formed on the first silicon nitride layer, the collar oxide, and the residual TEOS oxide layer. The second silicon nitride layer is etched anisotropically to form a silicon nitride sidewall on said collar oxide, subsequently, removing the residual TEOS oxide layer by wet etching.
When the residual TEOS oxide has been etched, the trench region is then etched using the silicon nitride sidewall as a barrier. A freshly excavated trench is formed, wherein the surface of the fresh trench is increased. A dopant layer is formed in the fresh trench region for doping ions over the fresh trench region of lower the silicon nitride sidewall to form a bottom cell plate. In the other embodiment, the fresh trench is formed after the steps of doping for increasing the surface of the trench.
The silicon nitride sidewall is removed. A dielectric film is formed on the bottom cell plate, the collar oxide, and the first silicon nitride layer, subsequently, a first conductive layer is formed on said dielectric film. The first conductive layer and the dielectric film are etched to a second level to expose a portion of the collar oxide, the exposed portion of the collar oxide is then etched by wet etching. A second conductive layer is formed on the first conductive layer and etched back to form a buried strap in the trench region.


REFERENCES:
patent: 5112771 (1992-05-01), Ishii et al.
patent: 5877061 (1999-03-01), Halle et al.
patent: 6015985 (2000-01-01), Ho et al.
patent: 6018174 (2000-01-01), Schrems et al.
patent: 6025245 (2000-02-01), Wei

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