Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1999-02-18
2001-01-30
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S788000, C438S692000, C438S778000, C438S783000, C438S710000
Reexamination Certificate
active
06180540
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to forming fluorosilicate glass (FSG) layers within microelectronics fabrications. More particularly, the present invention relates to methods for forming stabilized fluorosilicate glass (FSG) layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers. As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly more important within the art of microelectronic fabrication to form interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications microelectronic dielectric layers formed of low dielectric constant dielectric materials. Low dielectric constant dielectric materials are desirable for forming microelectronic dielectric layers formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications since such low dielectric constant dielectric materials provide, among other features, microelectronic fabrications with enhanced microelectronic fabrication speed and reduced patterned microelectronic conductor layer cross-talk.
For the purposes of the present disclosure, low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant (relative to vacuum) of preferably less than about 3.7, and more preferably from about 2.5 to about 3.5. For comparison purposes, conventional dielectric materials which are typically employed within microelectronic fabrications, such conventional dielectric materials including but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials, typically have dielectric constants in the range of from about 4.0 to about 9.0.
Of the low dielectric constant dielectric materials which may be employed for forming low dielectric constant dielectric layers within microelectronic fabrications fluorosilicate glass (FSG) low dielectric constant dielectric materials have recently received considerable interest and attention. Within the context of the present application, fluorosilicate glass (FSG) low dielectric constant dielectric materials are intended as non-stoichiometric silicon oxide dielectric materials which have incorporated therein a fluorine dopant at a concentration of from about 4 to about 7 atom percent. Such fluorosilicate glass (FSG) low dielectric constant dielectric materials typically have a dielectric constant of from about 3.5 to about 3.8. Fluorosilicate glass (FSG) low dielectric constant dielectric materials are generally of interest insofar as they may under certain circumstances be formed by employing comparatively minor modifications of methods which are conventionally employed for forming silicon oxide dielectric materials within microelectronic fabrications.
While low dielectric constant dielectric layers formed of fluorosilicate glass (FSG) dielectric materials are thus desirable within the art of microelectronic fabrication, low dielectric constant dielectric layers formed of fluorosilicate glass (FSG) dielectric materials are nonetheless not entirely without problems within the art of microelectronic fabrication. In particular, it is known in the art of microelectronic fabrication that low dielectric constant dielectric layers formed of fluorosilicate glass (FSG) dielectric materials are often chemically unstable incident to the incorporation therein of loosely bound mobile fluorine atoms. The loosely bound mobile fluorine atoms thus typically encountered within fluorosilicate glass (FSG) low dielectric constant dielectric materials are generally also susceptible to reaction with or transfer through various microelectronic layers typically employed within a microelectronic fabrication within which is formed a low dielectric constant dielectric layer formed of a fluorosilicate glass (FSG) low dielectric constant dielectric material to thus provide compromised operation of the microelectronic fabrication within which is formed such a low dielectric constant dielectric layer formed of a fluorosilicate glass (FSG) dielectric material.
It is thus towards the goal of forming within a microelectronics fabrication a low dielectric constant dielectric layer formed of a fluorosilicate glass (FSG) dielectric material with enhanced stability with respect to loosely bound mobile fluorine atoms that the present invention is more particularly directed.
Various methods have been disclosed within the art of microelectronic fabrication for forming dielectric layers with desirable properties within microelectronic fabrications.
For example, Lou, in U.S. Pat. No. 5,759,906, discloses a method for forming within a microelectronic fabrication a planarized inter-metal dielectric (IMD) layer comprising a low dielectric constant dielectric material comprising a spin-on-glass (SOG) dielectric material or a spin-on-polymer (SOP) dielectric material: (1) without directly planarizing the low dielectric constant dielectric material; and (2) while not exposing within a via formed through planarized inter-metal dielectric (IMD) layer the low dielectric constant dielectric material comprising the spin-on-glass (SOG) dielectric material or the spin-on-polymer (SOP) dielectric material. To realize the foregoing objects, there is first employed when forming the planarized inter-metal dielectric (IMD) layer a dielectric capping layer (which may be formed of a fluorosilicate glass (FSG) dielectric material) where the dielectric capping layer is partially chemical mechanical polish (CMP) planarized without planarizing the low dielectric constant dielectric material comprising the spin-on-glass (SOG) dielectric material or the spin-on-polymer (SOP) dielectric material. There is then also formed an annular dielectric spacer layer (which may also be formed of a fluorosilicate glass (FSG) dielectric material) into a via formed through the partially chemical mechanical polish (CMP) planarized dielectric capping layer and the underlying low dielectric constant dielectric material.
In addition, Guo et al., in U.S. Pat. No. 5,763,010, disclose a method for stabilizing a halogen doped silicon oxide layer, such as a fluorosilicate glass (FSG) layer, with respect to loosely bound migrating halogen atoms within the halogen doped silicon oxide layer. The method employs, prior to forming a diffusion barrier layer upon the halogen doped silicon oxide layer, a thermal annealing and degassing of the halogen doped silicon oxide layer at a temperature of from about 300 to about 550 degrees centigrade, and under the circumstances where the halogen doped silicon oxide layer is formed of a fluorosilicate glass (FSG) material, for a time period of from about 35 to about 50 seconds.
Further, Murugesh et al., in U.S. Pat. No. 5,811,356, discloses a method for reducing mobile ionic and metallic contaminants within a microelectronics layer, such as a microelectronics dielectric layer, formed within a microelectronics reactor chamber. The method employs seasoning the microelectronics reactor chamber by depositing a layer of an encapsulant material within the microelectronics reactor chamber at a bias radio frequency power density of greater than about 0.051 watts per square centimeter for a time period of greater than about 30 seconds.
Finally, Bhan et al., in U.S. Pat. No. 5,827,785, also discloses a method for forming within a microelectronics fabrication a halogen doped silicon oxide layer, such as a fluorosilicate glass (FSG) layer, with improved stability with respect to loosely bound mobile halogen atoms within the halogen doped silicon oxide layer. To realize that object, there is employed when forming the halogen doped silicon oxide layer a
Ackerman Stephen B.
Bowers Charles
Saile George O.
Smoot Stephen W.
Stanton Stephen G.
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