Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-11-30
2001-05-08
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06230292
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to methods for testing semiconductor devices.
2. State of the Art
Processed semiconductor wafers typically comprise an array of substantially isolated integrated circuitry which are individually referred to as “dice” or “chips”. The die comprise the finished circuitry components of, for example, memory circuits such as DRAM and SRAM chips.
After a semiconductor wafer has been fabricated, not all dice provided on the wafer prove operable, resulting in less than 100% yield. Accordingly, individual dice must be tested for functionality. The typical test procedure for DRAM or SRAM circuitry is to first etch the upper protective passivation layer to expose desired bonding pads on the individual dice. Thereafter, the wafer is subjected to test probing whereby the individual dice are tested for satisfactory operation. Inoperable dice are typically identified by an ink mark. After testing, the wafer is severed between the individual dice, and the operable, non-marked dice are collected.
Memory chips are typically designed with redundant memory cells used to replace identifiable, defective memory cells. The redundant cells are provided within an array of memory cells, and are designed to be fusibly linked with the array to replace any of the defective cells. This process can be carried out after this initial testing. These “corrected” dice are then added to the batch of “operable” die.
The “corrected” and “operable” individual dice are assembled in final packages of either ceramic or plastic. After packaging, the dice are loaded into burn-in boards which comprise printed circuit boards having individual sockets connected in parallel. The burn-in boards are then put into a burn-in oven, and the parts are subjected to burn-in testing. During burn-in, the dice are operated for a period of time at different temperature cycles, including high temperatures and accelerated voltages. The dice are stressed to accelerate their lives in an effort to determine when the dice are likely to fail. Manufacturers predict early failures, known as “infant mortalities”, to occur within a predetermined period of time of the burn-in cycle. Burn-in testing is conducted for a period of time sufficient to reveal infant mortalities. For example, if infant mortalities are expected to occur within 48 hours of bum-in testing, the burn-in tests can be completed within this time period.
According to the above testing procedures, the dice are subjected to a test before severing, and a second test after severing and packaging of the individual die. Under present testing conditions, completely defective dice are often discovered during the initial testing procedures. If possible, defective memory cells are replaced with redundant memory cells to correct the dice. The “operable” and “corrected” dice then undergo a burn-in testing cycle which is commonly a two-day event. Essentially, the bum-in testing discovers weaknesses in the chip which, while not completely defective, will inhibit normal operation, occasionally fail, or entirely fail within a short period of time after fabrication. Burn-in testing is designed to reveal these latent defects.
However, the bum-in testing stage occurs late in the manufacturing process after the dice have already been severed and individually packaged. At this stage, it is often too late to replace inoperable memory cells with redundant memory cells. Furthermore, for those dice which do not successfully pass the burn-in testing stage (i.e., due to some latent defect), the manufacturer has already incurred the expense of packaging defective dice. Another consideration is that the burn-in testing stage typically takes from 12 to 48 hours to discern whether a die is defective. While this is a reasonable time frame, it would be advantageous to have a shorter time frame.
The second test (i.e., after severing and packaging) also identifies dice which fail due to a weakness, typically due to a defect, but are not observable in the test probing phase described above.
Accordingly, it is desired to develop testing techniques which would reveal weaknesses or other latent defects at an earlier stage in the manufacturing process so that the manufacturer has an opportunity to correct the defect before severing and final packaging. It is also desirable to conduct such tests within a short time frame to further increase manufacturing efficiency and timeliness.
SUMMARY OF THE INVENTION
The present invention teaches circuitry and multiple methods for testing semiconductor devices to reveal weaknesses or other latent defects prior to assembly, and in a much shorter time frame than with conventional bum-in testing processes. The signal generation circuitry, preparatory and control circuitry described, and the test methods used stress the semiconductor device by purposefully altering one or any of: 1) the start times of the timing signals in relation to commencement of a cycle, 2) the durations of the timing signals, and 3) the voltage levels of the timing signals, to values outside the normal operating parameters of the device. In this way, if any weaknesses or defects are present within the device, the output of the device will reveal an error. The output of the device is then checked by analyzing circuitry to determine if the device has any weaknesses or defects by comparing the output with the input.
One significant advantage of this invention is that for each correctable weakness or defect discovered, a repair or replacement may occur prior to assembly to prevent the device from failing later. As a result, bum-in testing is conducted only on those chips which have proven satisfactory in the disclosed tests, significantly reducing the failure rate of the burn-in testing phase.
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Duesman Kevin G.
Heitzeberg Edward J.
Micro)n Technology, Inc.
Moise Emmanuel L.
TraskBritt
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