Abrading – Abrading process – Combined abrading
Reexamination Certificate
1999-05-25
2001-07-17
Hail, III, Jospeh J. (Department: 3723)
Abrading
Abrading process
Combined abrading
Reexamination Certificate
active
06261157
ABSTRACT:
TECHNICAL FIELD
This application relates to semiconductor fabrication and, more particularly, to chemical mechanical polishing of a semiconductor wafer.
BACKGROUND
Integrated circuits (ICs) typically are formed by depositing some combination of conductive, semiconductive, insulating, and barrier-forming materials on a semiconductor substrate, such as a doped silicon wafer. One common technique for producing an IC, known as “subtractive metallization,” involves depositing a conductive or semiconductive layer on the substrate and then etching away a portion of the conductive layer to form a conductive pattern. A barrier layer usually separates the conductive layer from the semiconductor substrate to protect the substrate from contamination by the conductive material. In most cases, additional conductive or semiconductive layers are deposited over the original conductive layer. Each pair of adjacent conductive layers is separated by an insulating layer which, like the original conductive layer, is patterned to allow ohmic contact between the conductive layers.
Another common technique for producing an IC, known as “Damascene metallization,” involves forming an insulating layer directly over the semiconductor substrate, etching the insulating layer to form an opening over a portion of the semiconductor substrate, depositing a barrier layer over the insulating layer and the opening, and then depositing a conductive material over the barrier layer. The opening in the insulating layer allows ohmic contact between the conductive layer and a portion of the semiconductor substrate. The barrier layer protects the semiconductor substrate from contamination by the conductive layer.
One problem with these semiconductor fabrication techniques is that etching the conductive layers produces unwanted topography on the surface of the semiconductor device for subsequent processing. Damascene processing has the potential of creating topography-free surfaces. The complexity of the topography increases with the number of additional layers. As a result, most semiconductor manufacturing processes include one or more planarization steps to remove topography from the surfaces of semiconductor devices.
Chemical mechanical polishing (CMP) is one very common type of planarization process. In general, a CMP process involves mounting the semiconductor device on a carrier or polishing head and pressing the surface of the device against a rotating polishing pad. A traditional slurry-based CMP process uses a standard polishing pad in combination with a liquid slurry that includes a chemically reactive agent and abrasive particles. Recently developed “slurryless” CMP processes use fixed-abrasive pads in conjunction with polishing liquids containing chemically reactive agents but no abrasive particles. A fixed-abrasive pad includes abrasive particles embedded within a containment media. A standard polishing pad has a durable surface with no embedded abrasive particles.
An effective CMP process not only provides a high polishing rate, but also provides a substrate surface that lacks small-scale roughness (i.e., is “finished”) and that lacks large-scale topography (i.e., is “flat”). The polishing rate, finish, and flatness associated with a particular CMP process are determined by several factors, including the type of pad and the type of slurry used, the relative speed between the semiconductor substrate and the polishing pad, and the amount of pressure that forces the semiconductor substrate against the polishing pad.
Planarization of a semiconductor device formed by Damascene metallization usually involves a conventional Damascene CMP process. Damascene CMP techniques use standard polishing pads and “selective” or “nonselective” slurries. Nonselective slurries attempt to polish the conductive layer and the barrier layer simultaneously, leaving a perfectly planarized surface on which only the insulating layer and the conductive material in the trenches of the insulating layer are exposed. However, current semiconductor fabrication techniques usually produce devices with nonuniformities in the conductive layer, which leads to uneven removal time across the surface of the device. This combined with CMP within-wafer-nonuniformity (WIWNU) can lead to significant variation across the wafer-in dishing and erosion. As a result, the insulating layer becomes exposed at some areas on the device while thin layers of barrier and conductive materials remain on other areas of the device. Moreover, because conventional nonselective polishing techniques remove insulating, barrier, and conductive materials at similar rates, these nonuniformities in the surface of the semiconductor device leads to a phenomenon known as “metal thinning.” Selective slurries cause dishing and erosion across the wafer.
SUMMARY
The inventors have developed a Damascene CMP technique that virtually eliminates dishing and large-scale topography from the polished surface, while achieving fast throughput. This technique trivializes nonuniformities in the conductive layer by ensuring that polishing does not begin on the barrier layer until all or almost all of the overlying conductive material is removed.
In some aspects, the invention involves planarizing a semiconductor device to remove surface topography. The semiconductor device includes a semiconductor layer formed on a substrate, an insulating layer formed over the semiconductor layer and patterned to expose a portion of the semiconductor layer, a barrier layer formed over the insulating layer and the exposed portion of the semiconductor layer, and an electrically conductive layer formed over the barrier layer. The semiconductor device is pressed against a first rotating polishing pad that has no embedded abrasive particles to remove a portion of the conductive layer that overlies both the barrier layer and the insulating layer. The semiconductor device is then pressed against a second rotating polishing pad that has embedded abrasive particles to expose a portion of the barrier layer that overlies the insulating layer. The device is then pressed against a third rotating polishing pad that has no embedded abrasive particles to remove the portion of the barrier layer that overlies the insulating layer.
In some embodiments, an electronic measurement device, such as a laser interferometer coupled to a digital computer, is used to monitor how much of the conductive layer remains over the barrier layer and the conductive layer. The semiconductor device is usually removed from the first polishing pad when a predetermined amount of the conductive layer remains over the barrier layer and the insulating layer. For example, for a semiconductor device in which the barrier layer has a thickness on the order of a few hundred angstroms (e.g., 200-300 Å) and the conductive layer has a thickness on the order of a few microns (e.g., 1.2 &mgr;m), some embodiments involve removing the semiconductor device from the first polishing pad when the conductive layer has a thickness on the order of a few hundred to a few thousand angstroms (e.g., 2000 Å). In certain embodiments, the barrier layer includes a material such as tantalum, the conductive layer includes a material such as copper, and the insulating layer includes an oxide material, such as silicon dioxide.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
REFERENCES:
patent: 5498199 (1996-03-01), Karlsrud et al.
patent: 5816891 (1998-10-01), Woo
patent: 5897426 (1999-04-01), Somekh
patent: 5913712 (1999-06-01), Molinar
patent: 6062954 (2000-05-01), Izumi
Bajaj Rajeev
Li Shijian
Ma Yutao
Redeker Fritz C.
White John M.
Applied Materials Inc.
Fish & Richardson
Hail, III Jospeh J.
Nguyen George
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