Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-24
2001-09-25
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S593000, C257S317000
Reexamination Certificate
active
06294429
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the manufacture of non-volatile memory devices, and more particularly to an improved method of forming a charge injection region on a floating gate of a memory cell.
2. Description of Related Art
In a non-volatile memory cell charge is stored on a floating gate comprised of a silicon body surrounded by a suitable insulator such as silicon dioxide. Typically, this floating gate is overlaid by a second conductive layer called the control gate which is connected to the circuit and has high voltage applied to it to cause charge to move across the insulating barrier.
One method to speed the process of removing charge from the floating body while keeping applied voltages low is to form a pointed feature on the body which enhances the electric field. In the simplest implementation of this idea, a square corner is formed when the body is defined and then the overlying conductor is shaped such that it wraps around this comer.
In Jenq, U.S. Pat. No. 5,278,087, a specific implementation of a source side injection NVRAM memory cell is disclosed. In this disclosure, a method to form injectors with an angle of less than the 90 degree square corner (and thus a higher electric field) is disclosed. In Jenq, a silicon layer is overlaid with a suitable oxidation blocking layer, e.g. silicon nitride, and an opening in this upper layer is made. The silicon is then oxidized. Due to the masking properties of the overlayer, and the fact that silicon oxidation grows “into” the silicon, a sloped recess is formed in the silicon film at the mask edge. The overlayer is then removed selectively to the silicon body and the silicon dioxide. Finally, the silicon layer is etched with an anisotropic dry etch such that what remains is the silicon dioxide layer with the portion of the silicon film beneath it. The resulting floating gate body will have a comer sharper than 90 degrees determined by the relative amount of oxidation and the specifics of the masking layer and oxidation process used.
“Scaling” is a necessary requirement of reducing costs of semiconductor components particularly in the field of very large scale integration (VLSI). The most obvious aspect of “scaling” is a reduction of the lengths and widths of specific features of semiconductor devices which usually requires a vertical scaling of the thickness of the films which are used to make the device. When a silicon film is oxidized it tends to oxidize faster along grain boundaries. In some cases the film will be broken up into individual islands. The oxidation may even proceed to the underlying single crystal silicon substrate which is the conductive channel for the device. The net result is that at some point in the scaling of the memory cell the oxidation process used to form the injection point becomes non-manufacturable.
A difficulty of Jenq is that the nature of the interface between the original silicon film and the overlying oxidation mask is critical. Any oxide, such as may grow in the room air or during insertion into a deposition tool used to produce the masking layer, provides an unintended path for oxidation and may enlarge and/or distort the shape of the final structure.
A further limitation of Jenq is that the resulting floating gate structure must have silicon dioxide as the insulator between itself and the control gate (since oxidation is used to provide this insulation) and the total thickness of the insulating layer is inherently restricted by the thickness of the silicon film (e.g. in the extreme limited to the result of total consumption of the film by oxidation).
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of forming a charge injection region on a floating gate.
It is another object of the present invention to provide a method of forming sharp corners in the gate material of a floating gate structure.
A further object of the invention is to provide a method of forming sharp corners on a floating gate of a memory cell with the minimum geometry allowed by lithography.
It is yet another object of the present invention to provide a method of alleviating oxidation size limitations on a floating gate of a memory cell.
It is yet another object of the present invention to provide a method of alleviating limits on the choice of insulator materials in forming a floating gate on a memory cell.
Still other objects and advantages of the invention will be in part obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of forming a charge injection region on a floating gate of a semiconductor structure. The preferred embodiment of the method comprises providing a semiconductor structure having a plurality of layers and defining a floating gate region in the structure. A charge injection region is formed along an edge of the floating gate region by a first etching process and the floating gate is formed on the substrate. In the preferred embodiment the semiconductor structure comprises a first insulating layer over a semiconductor substrate, a first semiconductor layer over the insulating layer and a dielectric layer over the first semiconductor layer. It is preferred that the first insulating layer is a floating gate oxide, the first semiconductor layer is a floating gate silicon and the dielectric layer is silicon nitride.
The preferred embodiment of the method comprises defining the floating gate region by forming an opening in the dielectric layer to expose the first semiconductor layer. It is preferred that the opening be formed by first applying a resist pattern mask to the top of the dielectric layer, developing the resist pattern mask to expose portions of the dielectric layer, and then removing the exposed portions of the dielectric layer to form the opening. A reactive ion etch selective to the first semiconductor layer may be used to remove the exposed portions of the dielectric layer and to form the opening.
In the preferred method the first etching process comprises etching a trench in the first semiconductor layer. The trench has a bottom and a pair of sidewalls and may extend into the semiconductor layer to a depth in the range of approximately 10-20 nanometers. It is preferred to form the trench using an isotropic plasma etch, and it is most preferred to form the trench by etching slightly into the first semiconductor layer using a less nitride to silicon etch chemistry within approximately 50% isotropy.
The preferred method also comprises depositing a layer of a second insulating material into the trench and opening and removing the remaining portions of the dielectric layer to form a plug of the second insulating material over the first semiconductor layer. In the preferred embodiment, the second insulating layer is a chemical vapor deposition oxide. After depositing the layer of second insulating material in the trench and opening, it is preferred to polish the layer of the second insulating material to the top of the dielectric layer. The plug may be used as a mask over the first semiconductor layer and the exposed portions of the first semiconductor layer are removed to form the floating gate.
In another aspect, the present invention comprises a method of forming a point on a floating gate for electron injection. The method comprises the steps of: (a) providing a semiconductor substrate; (b) depositing a layer of a gate oxide material over the substrate; (c) depositing a layer of a gate silicon material over the gate oxide layer; (d) depositing a layer of silicon nitride over the gate silicon layer; (e) forming an opening in the silicon nitride layer to expose the gate silicon layer; (f) etching the gate silicon layer to form a trench having a bottom and pair of sidewalls with each of the sidewalls defining a sharp angle to a
Lam Chung H.
Martin Dale W.
Willets Christa R.
Bowers Charles
DeLio & Peterson LLC
International Business Machines - Corporation
Reynolds Kelly M.
Sabo William D.
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