Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-16
2001-09-18
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S659000, C257S660000
Reexamination Certificate
active
06291285
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for protecting the gate oxide layer of a MOS device. More particularly, the present invention relates to a method that utilizes a shielding layer to protect the gate oxide layer against processing damages.
2. Description of Related Art
In the manufacturing the gate of a MOS device, a thin gate oxide layer is first formed over a semiconductor substrate. Thereafter, a polysilicon layer that acts as a gate electrode is formed over the gate oxide layer. Next, a dielectric layer is formed over the gate electrode and the substrate to form multi-layered metallic interconnects. The dielectric layer serves as a layer of insulating material separating the metallic interconnects from the gate electrode. Since the dielectric layer lies between the gate electrode and the first metallic interconnect, the dielectric layer is also known as an inter-layer dielectric (ILD) layer.
In general, a high-density plasma (HDP) etching operation is normally used to form metallic interconnects in the ILD layer. The HDP etching technique is preferred because ultimately a trench having a better gap-filling capacity is formed. However, during a HDP etching operation, quality of the gate oxide layer in the MOS device may be affected. The two main reasons are:
1. Due to the attraction effect of the gate electrode of a gate structure, charged particles in the high-density plasma penetrates through the dielectric layer into the gate electrode. Moreover, a portion of the charged particles are energetic enough to enter the gate oxide layer. Any movement of charged particles inside the gate oxide layer destroys the compact internal structure. Hence, defects may form within the gate oxide layer.
2. When an HDP etching operation is carried out, strong ultraviolet or short wavelength radiation are generated due to the bombardment of the substrate by highly charged particles within the plasma. Ultraviolet or short-wavelength radiation has a very high penetrating power and is able to pass through the dielectric layer surrounding the gate oxide layer. Ultimately, a portion of the light is absorbed by the gate oxide layer. Since ultraviolet rays or short-wavelength radiation contains a lot of energy, the electric charges originally trapped within the gate oxide layer, at the interface between the gate oxide layer and the substrate and at the interface between the gate oxide layer and the gate electrode, can be activated to produce a large quantity of excited electron-hole pairs. These excited electron-hole pairs move about destroying the fine crystalline structure within the gate oxide layer.
In fabricating semiconductor devices in the deep sub-micron range, the quality of the gate oxide layer is very important. Since a gate oxide layer can have a thickness as small as 100 Å, any attraction of charged particles or irradiation by ultraviolet or short-wavelength radiation creates many defects within the gate oxide layer. Once the gate oxide layer contains defects, quality of the semiconductor device can be affected and its product yield can be lowered.
The conventional method of minimizing damages inflicted upon the gate oxide layer is to form a protective diode that links the gate oxide layer with the substrate. As soon as charged particles reach the gate oxide layer, these charged particles are led to the protective diode and then drained away via the substrate. Hence, the protective diode is able to reduce the flow of charges within the gate oxide layer, and prevent much of the damage due to the attraction effect. However, the protective diode is unable to protect the gate oxide layer against destructive ultraviolet rays or other short-wavelength radiation. Therefore, any short-wavelength radiation or ultraviolet light generated by high-density plasma can still penetrate into the gate oxide layer.
In light of the foregoing, there is a need to provide a method of minimizing the damages inflicted upon the gate oxide layer of a MOS device due to plasma etching.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method for protecting the gate oxide layer of a MOS device against damages caused by charged particles, ultraviolet rays or short wavelength radiation.
In another aspect, the purpose of the invention is to provide a method for monitoring the degree of damage to the gate oxide layer caused by plasma etching. Hence, proper settings of all the parameters needed to carry out a plasma etching operation so that a high-quality gate oxide layer can be obtained are available.
To achieve these and other advantages and in accordance with the purpose of the inventions as embodied and broadly described herein, the invention provides a method for protecting the gate oxide layer. The method includes the steps of providing a gate structure above a substrate, wherein the gate structure further comprises a gate oxide layer and a gate electrode. An inter-layer dielectric layer is formed over the substrate and the gate structure, and then a shielding layer is formed over the inter-layer dielectric layer. A protection diode is formed to link the shielding layer and the substrate.
The method of this invention is capable of preventing the damaging effect inflicted upon the gate oxide layer due to the attraction of charged particles by the gate electrode. In addition, the method is also capable of protecting the gate oxide layer against radiation damage by ultraviolet and other short wavelength radiation generated by high-density plasma. The shielding layer is able to block charge particles as well as any harmful ultraviolet or short-wavelength radiation. This is because charged particles or harmful radiation generates electric charges on entering the shielding layer. The electric charges are then channeled away from the shielding layer to the substrate via the protection diode. With all the energetic charged particles and harmful radiation screened by the shielding layer, quality of the gate oxide layer can be maintained.
Furthermore, by monitoring the quantity of electric charges flowing through the protection diode, data regarding the amount of ultraviolet light or short-wavelength radiation produced by the plasma can be obtained. Thus, parameters for operating a plasma etching station can be adjusted according to the data, and a gate oxide layer having the optimal quality can be produced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5497345 (1996-03-01), Cappelletti
Huang-Lu Shiang
Wang Mu-Chun
Berezny Nema
Bowers Charles
Charles C. H. Wu & Associates
United Microelectronics Corp.
Wu Charles C. H.
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