Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-09
2001-09-04
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S516000, C438S530000, C438S585000, C438S769000, C438S770000, C438S775000, C438S787000, C438S791000
Reexamination Certificate
active
06284580
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a MOS transistor, and more particularly to a method for manufacturing a MOS transistor having excellent electrical characteristics.
2. Description of the Related Art
For a semiconductor substrate for a LSI circuit with high density integration of MOS transistors, a silicon semiconductor substrate is generally used. A possible way to improve the operating speed of this LSI circuit is to increase the electrostatic capacity between a gate formed on a gate oxide film in the active region of the semiconductor substrate for the MOS transistor and the active region below the gate.
This electrostatic capacity is connected with the thickness of the gate oxide film and the dielectric constant of the material of the gate oxide film. To take an example, by using tantalum oxide (Ta
2
O
5
) having a high specific dielectric constant of about 25 to form the gate oxide film, the electrostatic capacity can be increased without making the gate oxide film so thin as to cause a problem of stray current due to the thinning of the gate oxide film.
Meanwhile, the gate oxide film consisting of tantalum oxide is formed in an atmosphere of oxygen gas. For this reason, a silicon oxide film (SiO
2
) with a low dielectric constant is formed between the tantalum oxide and the silicon semiconductor substrate, and this silicon oxide film impedes the increase of the electrostatic capacity.
Therefore, it has been proposed to adopt a multi-layered gate oxide film consisting of a silicon nitride layer and a tantalum oxide layer, made by first forming on the active region a silicon nitride layer (Si
3
N
4
) that shows a higher dielectric constant than that of the oxide film and inhibits the growth of the silicon oxide and then forming a tantalum oxide layer on the silicon nitride layer (e.g., JP-A-07-167008).
As the active region is covered with the silicon nitride layer before the tantalum oxide layer is formed on the active region of the silicon substrate, the silicon nitride layer prevents oxygen from penetrating into the silicon substrate during the formation of tantalum oxide layer on the silicon nitride layer. Therefore, the growth of a silicon oxide layer is inhibited, making it possible to prevent a decrease in the electrostatic capacity due to the growth of the silicon oxide layer and thus secure a desired electrostatic capacity.
As technique for forming a silicon nitride layer on a silicon semiconductor substrate as mentioned above, there are methods such as RTN (Rapid Thermal Nitrization) for directly nitrizing a silicon semiconductor substrate in an ammonia gas atmosphere (JP-A-05-167008), LPCVD (low-pressure CVD, JP-A-04-269859), Jet Vapor Deposition (by S. Mahapatra et al., 1999 VLSI Tech. Dig. P.79) and a nitrizing method using a high density plasma (Katsuyuki Sekine et al. 1999 VLSI Tech. Dig. P.115).
However, any of those methods uses ammonia (NH
3
) as a nitrizing gas and by heat treatment in an ammonia gas atmosphere, hydroxyl groups (OH) produced by combinations of oxygen atoms from a naturally oxidized film on the semiconductor substrate with hydrogen atoms from the ammonia are introduced into the gate oxide film. The OH groups in the gate oxide film act as a charge trap, resulting in deterioration of the electrical characteristics of the MOS transistor.
Therefore, the object of the present invention is to provide a method for manufacturing a MOS transistor capable of improving its operation speed by increasing the electrostatic capacity without incurring the deterioration of electrical characteristics caused by a charge trap.
SUMMARY OF THE INVENTION
To solve the above problem, the present invention adopts the following configuration.
According to the present invention, there is provided a method for manufacturing a MOS transistor having a gate oxide film formed on an active region of a silicon semiconductor substrate, the gate oxide film consisting of a silicon nitride layer for inhibiting the penetration of oxygen into the silicon substrate and a high dielectric oxide layer with higher dielectric constant than that of the silicon nitride layer, comprising the steps of pretreatment for forming a silicon oxide film with nitrogen atoms on the active region; segregation for causing a silicon nitride layer to segregate out at an interface between the silicon substrate and the silicon oxide film by heat-treating the pretreated silicon substrate in an inert gas atmosphere; forming a high dielectric film by removing the unnecessary silicon oxide film on the silicon nitride layer to expose a segregated silicon nitride layer and depositing a high dielectric oxide layer on the exposed silicon nitride layer; and forming a gate on the gate oxide film consisting of the silicon nitride layer and the high dielectric oxide layer.
In the above-mentioned manufacturing method according to the present invention, by the above-mentioned segregation process, a silicon nitride layer segregates out at the interface between the nitrogen-containing silicon oxide formed on the active region by the pretreatment and the silicon substrate. The unnecessary silicon oxide film on is removed, and a high dielectric oxide layer with a higher dielectric constant than that of the silicon nitride layer is formed on the exposed silicon nitride layer. Thus, a multi-layered gate oxide film consisting of the silicon nitride layer and the high dielectric oxide layer has been formed, and then a gate is formed on top of the gate oxide film.
The silicon nitride layer formed by segregation does not include impurities such as hydroxyl groups and has had the unnecessary silicon oxide film removed. Therefore, even if hydroxyl groups that act as a charge trap were formed in the silicon oxide film, a charge trap, which used to occur heretofore, is not formed in the gate oxide film consisting of the silicon nitride layer and the high dielectric oxide layer on the silicon nitride film.
Therefore, according to the present invention, it is possible to produce a MOS transistor free from deterioration of characteristics caused by charge traps in the gate oxide film.
The high dielectric oxide layer may be formed in an oxygen gas atmosphere.
As the above-mentioned pretreatment, it is possible to adopt an annealing process in a nitrogen oxide gas atmosphere free of ammonia gas. As an alternative to the annealing process, a process may be adopted which comprises a nitrogen ion injection step for introducing nitrogen ions into the active region and a heat-treating step for forming the silicon oxide film. In comparison with the pretreatment using ammonia gas, those kinds of pretreatment are preferred because they do not include ammonia gas and thus securely prevent the generation of hydroxyl groups that act as charge traps.
For the segregation process, an annealing process by rapid thermal annealing (RTA) may be adopted. By adopting this rapid thermal annealing process, the silicon nitride layer can made to segregate out more efficiently at the interface of the silicon oxide film and the silicon substrate.
REFERENCES:
patent: 4-269859 (1992-09-01), None
patent: 5-167008 (1993-07-01), None
patent: 10-135207 (1998-05-01), None
patent: 10-209449 (1998-08-01), None
patent: 11-67760 (1999-03-01), None
Yider Wu et al., “Ultrathin Nitride/Oxide (N/O) Gate Dielectrics For p+-poly Gated PMOSFETs Prepared by a Combined Remote Plasma Enhanced CVD/Thermal Oxidation Process,” Extended Abstracts of the 1998 International Conference on Solid State Devices and Materials, Hiroshima, 1998, pp. 106-107.
K. Sekine et al., “High-integrity Ultra-thin Silicon Film Grown at Low Temperature for Extending Scaling Limit of Gate Dielectric,” 1999 Symposium on VLSI Technology Digest of Technical Papers, pp. 115-116.
S. Mahapatra et al., “100 nm Channel Length MNSFETs using A Jet Vapor Deposited Ultra-thin Silicon Nitride Gate Dielectric,” 1999 Symposium on VLSI Technology Digest of Technical Papers, pp. 79-80.
Frank Robert J.
OKI Electric Industry Co., Ltd.
Pham Long
Venable
Wood Allen
LandOfFree
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