Method of making damascene flash memory transistor

Details Method of making damascene flash memory transistor Method of making damascene flash memory transistor

1999-11-18

2001-05-08

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S594000, C438S653000

Reexamination Certificate

active

06228716

ABSTRACT:

FIELD OF THE INVENTION
This invention is a processing method for forming an MOS flash memory transistor wherein both a floating gate and a control gate are self aligned to the transistor channel region in both the width and length directions, and wherein metal interconnection lines make borderless connections to the control gate and to the source and drain diffusions. The method does not require any defect generating heavy oxidation of the silicon.
BACKGROUND OF THE INVENTION
MOS silicon gate technology defines an MOS flash memory transistor location by a field oxide opening, and defines the transistor channel location by a polysilicon floating gate overlying this opening, and a polysilicon control gate overlying and aligned to the floating gate. The width of the floating gate determines the channel length L of the transistor, and the width of the field oxide opening determines the channel width W of the transistor. The floating gate length is made longer than the channel width W to allow for misalignment tolerance. For a flash memory transistor with a sub micron channel width this tolerance can be almost as large as the width W. This problem severely limits the layout density of flash memory arrays. As shown in
FIG. 1A
, the spacing between transistors in the width direction can be no closer than two overlaps
15
plus the spacing
16
between floating gates
12
in the width direction.
Another important concern when designing a flash memory transistor is the coupling capacitance Ccf between the control gate and the floating gate. It is desirable to make Ccf larger than the tunneling capacitance Cfs between the floating gate and the substrate. As shown in
FIG. 1B
, Ccf is the capacitance between control gate
14
and floating gate
12
separated by dielectric
13
, and Cfs is the capacitance between floating gate
12
and the substrate separated by tunneling dielectric
11
. As a result of the overlaps
15
, It is apparent that the area of control gate
14
is only somewhat larger than the area of floating gate
12
. And, since dielectric
11
needs to be very thin for electron tunneling to occur, it is very difficult to make dielectric
13
much thinner than dielectric
11
, resulting in Ccf only being somewhat larger than Cfs.
SUMMARY OF THE INVENTION
The present invention is a method for forming an MOS flash memory transistor wherein its floating gate is self aligned to the transistor channel region in both the width and the length directions. As shown in
FIG. 2A
, floating gate transistors
20
can be as close in the width direction as the isolation spacing of N diffusions. As shown in
FIGS. 2B and 2C
, the overlap
25
of the floating gate
22
is in the vertical direction on four sides of the control gate
24
. Therefore It is possible to have a large ratio of coupling capacitance Ccf to tunneling capacitance Cfs, limited only by the vertical height
25
.
In addition, this invention:
1—Allows the use of a control gate made from metal or other conductors.
2—Creates totally planar surfaces for all masking levels, which facilitates photo masking of very narrow and closely spaced features.
3—Minimizes substrate defects by not using Local Oxidation of Silicon (LOCOS), or Shallow Trench Isolation (STI).


REFERENCES:
patent: 5907781 (1999-05-01), Chen et al.
patent: 6133096 (2000-10-01), Su et al.

Affiliated with

Also associated with

Rating

Method of making damascene flash memory transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making damascene flash memory transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making damascene flash memory transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2508037