Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-31
2001-03-27
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S141000, C257S156000, C257S173000, C257S355000, C257S360000, C257S378000, C257S389000, C257S463000, C257S501000, C257S546000, C257S591000, C257S655000
Reexamination Certificate
active
06207997
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an antistatic circuit. More particularly, it relates to a thin film transistor for an antistatic circuit of a semiconductor device which may prevent junction-leakage currents caused by electrostatic discharge (ESD), and further relates to a method for fabricating such a transistor.
2. Description of the Prior Art
The discharge of possibly volts of static electricity occurs during IC handling even with proper precautions, and can damage the circuit sufficiently, causing immediate failure or damage to the device. Thus, much research and development have been devoted to methods for preventing electrostatic discharge (ESD) failures. An increase in leakage currents of input and output pads in field effect transistors, bipolar transistors, N spreading resistance, and n+ junction regions of active transistors adversely affect the reliability of semiconductor devices such as dynamic random access memories (DRAM), static random memories (SRAM), etc.
The junction leakage currents result from the concentration of electric fields on the region where the junction is formed, the junction failure created during As ion (n+ source/drain high density ion) implantation, and the loss of oxide films for sidewall spacers of gate electrodes caused by etching during the fabrication process of a lightly-doped drain structure (LDD) NMOS transistor.
A conventional antistatic circuit for a semiconductor device will be described referring to FIG.
1
.
The conventional antistatic circuit of
FIG. 1
includes a first field effect transistor FT
11
and a second field effect transistor PT
12
respectively coupled to supply voltage Vcc and group Vss, a resistor Rs, and an active transistor AT
11
(or NMOS gate diode).
A conventional antistatic circuit of
FIG. 1B
is realized through a first npn bipolar transistor BT
11
and a second npn bipolar transistor BT
12
, rather than first field effect transistor FT
11
and second field effect transistor FT
12
and FIG.
1
A's circuitry.
In the meantime, FIG.
1
C's circuitry structure is substantially similar to that of FIG.
1
B's antistatic circuit except that FIG.
1
C's circuitry is realized through a third npn bipolar transistor BT
13
having a base connected to ground Vss, rather than second npn bipolar transistor BT
12
of FIG.
1
B's circuitry.
An antistatic circuit of
FIG. 2
includes a pull-up NMOS active transistor PU
2
coupled with supply voltage Vcc and a pull-down NMOS active transistor PD
2
coupled with ground Vss with respect to an output pad
21
.
The following description relates to the circuitry structure of a conventional antistatic circuit. Attention is now invited to
FIGS. 3A and 3B
.
FIG. 3A
is a schematic view of a field effect transistor for a conventional antistatic circuit, and shows active regions
30
, N+ source/drain high-density impurity diffused regions
34
, metal gate electrodes
36
, and metal contacts
37
.
Referring to
FIG. 38
, the conventional field affect transistor includes wells
31
formed on a silicon substrate, insulating layers
32
for electrical isolation between electrodes formed in each first interior of well
31
, low-density impurity diffused layers
33
respectively formed between insulating layers
32
. N+ source/drain high-density diffused layers
34
. Interlevel insulating layers
35
formed on insulating layers
32
for electrical isolation between electrodes and low-density impurity diffused layers
33
, and metal gate electrodes
36
formed on low-density impurity layers
33
and interlevel insulating layers
35
.
The following description concerns a method for fabricating the above-mentioned field effect transistor for a conventional antistatic circuit.
As mentioned above,
FIG. 3A
is a schematic plane view of the field effect transistor, and
FIG. 1B
is a sectional view of the field effect transistor as taken along arrows A A′ of FIG.
3
A.
The steps in the manufacture of the field effect transistor begin with forming well
31
on a silicon substrate. Insulating layer
32
for electrical isolation between electrodes is grown within well
31
to form active region
30
and a region for electrical isolation between electrodes.
Low-density ions are implanted into both sides of insulating layer
32
for electrical isolation between electrodes to form low-density impurity diffused layer
33
, and N+ source/drain high-density ions are implanted into low-density impurity diffused layer
33
to form N+ source/drain high-density impurity diffused region
34
. Interlevel insulating layer
35
and metal gate electrode
36
are formed on insulating layer
32
and low-density impurity diffused layer
33
in serial order.
Junctions created in regions A become weak through the above fabrication steps, and there is potential failure due to As ion implantation.
FIGS. 4A and 4B
depict an active transistor for a conventional antistatic circuit.
FIG. 4A
is a plane view of the active transistor for a conventional antistatic circuit, and illustrates an active region
60
, an N+ source/drain high-density impurity diffused region
64
, and a gate electrode
66
.
FIG. 4B
is a sectional view of the active transistor shown in FIG.
4
A.
The conventional active transistor includes p-type wells
61
formed on a silicon substrate, insulating layers
62
for electrical isolation between electrodes formed within p-type wells
61
, and a gate electrode
66
formed on insulating layer
62
. The active transistor of
FIG. 4B
also includes a low-density impurity diffused layer
63
interposed between insulating layers
62
, an oxide film
65
for sidewall spacers formed on sidewalls or gate electrode
66
and insulating layer
62
, and an N+ source/drain high-density impurity diffused region
64
formed in low-density impurity diffused layer
63
.
The following description concerns a method for fabricating the above-mentioned active transistor for a conventional antistatic circuit.
Referring to
FIGS. 4A and 4B
, well
61
is formed on a silicon substrate, and insulating layer
62
for electrical isolation between electrodes is grown within well
61
to form active region
60
and a region for electrical isolation between electrodes. A gate oxide layer and gate electrode
66
are formed on insulating layer
62
in serial order.
Subsequently, low-density ions are implanted into both sides of insulating layer
62
for electrical isolation between electrodes to form low-density impurity diffused layer
63
. Oxide film
65
for sidewall spacers is then formed on insulating layer
62
and gate electrode
66
. As ions are implanted into low-density impurity diffused layer
63
to form N+ source/drain high-density impurity S diffused region
64
.
Junctions created in the regions A are weakened through As ion implantation, and a crossing of insulating layer
62
and gate electrode
66
is also deteriorated by As ion implantation to create region B.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a thin film transistor for an antistatic circuit of a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
It is an object of the present invention to provide a thin film transistor for an antistatic circuit of a semiconductor device which can prevent junction leakage currents caused by electrostatic discharge (ESD).
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a thin film transistor for an ant
Jeong Jae Goan
Park Gun Woo
Clark Sheila V.
Hyundai Electronics Industries Co,. Ltd.
Townsend and Townsend / and Crew LLP
Warren Matthew E.
LandOfFree
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