Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-10
2001-05-08
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S275000, C438S296000, C438S297000
Reexamination Certificate
active
06228708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a mixed-mode device. More particularly, the present invention relates to a method of manufacturing a high voltage mixed-mode device.
2. Description of the Related Art
A mixed-mode circuit typically includes a circuit comprising both digital and analog devices on a logic area of a semiconductor chip. The digital devices include inverters, and adders, and the analog devices include amplifiers and analog-to-digital converters. The digital and analog devices further comprise elementary devices such as MOS transistors and capacitors.
FIGS. 1A through 1D
are schematic, cross-sectional views of the conventional process for manufacturing a mix-mode device.
First, as shown in
FIG. 1A
, a substrate
100
is provided. The substrate
100
comprises an active region
101
and a field oxide layer
102
. An oxide layer
104
is formed on the active region
101
. Using chemical vapor deposition, a conductive layer
106
such as a polysilicon layer is formed on the oxide layer
104
and the field oxide layer
102
.
As shown in
FIG. 1B
, the conductive layer
106
is patterned to form a conductive layer
106
a
as a bottom electrode of a capacitor on the field oxide layer
102
.
As shown in
FIG. 1C
, the oxide layer
104
is removed. A thermal oxidation step is used to form a gate oxide layer
108
on the substrate
100
and an oxide layer
110
on the surface and the sidewall of the bottom electrode
106
a
. The oxide layer
110
is used as an inter-polysilicon dielectric layer of the capacitor. A conductive layer
112
such as a polysilicon layer is conformally formed over the substrate
100
.
As shown in
FIG. 1D
, the conductive layer
112
is patterned to form an upper electrode
112
a
on the field oxide
102
and a conductive layer
112
b
on the oxide
108
over the active region
101
. The conductive layer
112
b
is a gate of the transistor.
In the prior processes for manufacturing the transistor gate and the capacitor in the mixed-mode device, only a low-voltage transistor gate on the active region and a capacitor on the field oxide layer are formed. The goal of forming a mixed-mode device comprising both high and low voltage transistors, and capacitors is not attainable, especially for the sub-micron fabrication process.
SUMMARY OF THE INVENTION
It is therefore an objective of the invention to provide a method of manufacturing a high voltage mixed-mode device. The capacitor and the gates of the low voltage transistor and the high voltage transistor are formed by the same fabricating step.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a high voltage mixed-mode device. A substrate comprising an isolation region, a first active region and a second active region is provided. A first oxide layer is formed on the first active region and the second active region, wherein the thickness of the first oxide layer on the second active region is thicker than that on the first active region. A first conductive layer is formed on the first oxide layer and the isolation region. A patterned second oxide layer is formed on the first conductive layer. A patterned second conductive layer is formed on the second oxide layer and the first conductive layer. The first conductive layer is patterned to form a low-voltage transistor gate on the first active region, a high voltage transistor gate on the second active region and a capacitor on the isolation region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5691217 (1997-11-01), Honeycutt
patent: 5893737 (1999-04-01), Takahi et al.
patent: 5953599 (1999-09-01), El-Diwany
patent: 6087225 (2000-07-01), Broner et al.
Fourson George
Garcia Joannie A.
United Microelectronics Corp.
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