Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-14
2001-08-07
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000
Reexamination Certificate
active
06271072
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory, and more particularly, a method of fabricating a dynamic random access memory having a storage node with five polysilicon bars.
(2) Description of the Prior Art
In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, the reduction in cell size results in a decrease in storage capacitance leading to reliability drawbacks, such as a lowering of source/drain ratio and undesirable signal problems. In order to achieve the desired higher level of integration, the technology must keep almost the same storage capacitance on a greatly reduced cell area.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities have included the use of a stacked cylindrical capacitor design in which the capacitor cell uses the space over the device area for the capacitor plates. In U.S. Pat. No. 5,436,187 to Tanigawa, a cylindrical capacitor is formed using spacers. U.S. Pat. No. 5,733,808 to Tseng forms a cylindrical capacitor by laterally etching a resist mask and then etching out the central portion of a polysilicon layer. U.S. Pat. No. 5,712,202 to Liaw et al shows a process for a double-walled cylindrical capacitor using spacers and an etch back process. U.S. Pat. No. 5,821,139 to Tseng and U.S. Pat. No. 5,721,154 to Jeng show processes for forming double-walled cylindrical capacitors using spacers. U.S. Pat. No. 5,753,420 to Misium teaches a process of silylating an unexposed photoresist layer leaving a residue to be used in etching a capacitor plate with peaks. U.S. Pat. No. 5,753,419 to Misium uses silylated photoresist to etch a wave pattern into a polysilicon layer to form a storage node. U.S. Pat. No. 5,362,606 to Hartney et al discloses the use of silylated photoresist to form a pattern.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an improved and very manufacturable process for producing a memory cell capacitor with increased capacitance.
A further object of the invention is to provide a method for forming a capacitor having a storage node with five polysilicon bars.
Yet another object is to provide a method for forming a capacitor having a storage node with five polysilicon bars by using a silylated photoresist process.
According to the objects of the invention, a method is described for forming a dynamic random access memory cell with an increased capacitance capacitor having a storage node with five polysilicon bars by using a silylated photoresist process. Semiconductor device structures are provided in and on a semiconductor substrate wherein the semiconductor device structures include a node contact region within the semiconductor substrate. A first dielectric layer is deposited overlying the semiconductor device structures and planarized. A contact opening is made through the first dielectric layer to the node contact region. A first layer of polysilicon is deposited overlying the first dielectric layer and filling the contact opening. A photoresist mask is formed overlying the portion of the first polysilicon layer over the node contact region. The photoresist mask is silylated to form a top silylated photoresist portion and silylated photoresist sidewalls on the surfaces of the photoresist mask. The top silylated photoresist portion is removed. The unsilylated photoresist mask is removed. A portion of the first polysilicon layer is etched away where it is not covered by the silylated photoresist sidewalls thereby forming two first polysilicon bars underlying the silylated photoresist sidewalls and leaving a second thickness of the first polysilicon layer smaller than its first thickness. The silylated photoresist sidewalls are removed. A second dielectric layer is deposited overlying the first polysilicon layer and is etched back anisotropically to form inner spacers on the inner sides of the two first polysilicon bars and outer spacers on the outer sides of the two first polysilicon bars wherein there is a gap between the inner spacers. A second polysilicon layer is deposited overlying the first polysilicon layer, first polysilicon bars, and spacers. The first and second polysilicon layers are anisotropically etched back to form two second polysilicon bars on the outside edges of the outer spacers and a third second polysilicon bar filling the gap between the inner spacers and to form a T-shaped first polysilicon layer wherein the vertical portion of the T-shape lies within the node contact opening and wherein the horizontal portion of the T-shape overlies the vertical portion and underlies the two first polysilicon bars and the three second polysilicon bars. The dielectric spacers are removed whereby the T-shaped first polysilicon layer and the two first polysilicon bars and three second polysilicon bars make five polysilicon bars which together form a storage node of the capacitor. A capacitor dielectric layer is deposited over the first dielectric layer and the storage node. A third polysilicon layer is deposited overlying the capacitor dielectric layer wherein the third polysilicon layer forms the top electrode of the capacitor. The third polysilicon layer and the capacitor dielectric layer are patterned to complete formation of a DRAM with capacitor.
REFERENCES:
patent: 5362606 (1994-11-01), Hartney et al.
patent: 5436187 (1995-07-01), Tanigawa
patent: 5712202 (1998-01-01), Liaw et al.
patent: 5721154 (1998-02-01), Jeng
patent: 5733808 (1998-03-01), Tseng
patent: 5753419 (1998-05-01), Misium
patent: 5753420 (1998-05-01), Misium
patent: 5821139 (1998-10-01), Tseng
patent: 5849617 (1998-12-01), Wu
patent: 5953608 (1999-09-01), Hirota
patent: 5956587 (1999-09-01), Chen et al.
patent: 6080621 (2000-06-01), Wang et al.
patent: 6093601 (2000-07-01), Tsai et al.
patent: 6124162 (2000-09-01), Lin
Ackerman Stephen B.
Chaudhuri Olik
Coleman William David
Pike Rosemary L. S.
Saile George O.
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