Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1998-11-13

2001-06-26

Decady, Albert (Department: 2184)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06253342

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit having a micro-computer and a logic for a user. More particularly, it relates to an integrated circuit in which a new logic can be added to the micro-computer over a bus. The term ‘logic’ used herein denotes a ‘logic unit’ in general.
RELATED ART
If, in a conventional integrated circuit of this sort, a pre-existing micro-computer and an additional logic for a user are connected to each other, a logic dedicated for connection is provided between the micro-computer and an external bus of the additional logic for the user, one of the two being connected to an external bus/port changeover terminal of the micro-computer and the other being connected to an external bus of the additional logic for the user, as described in e.g., JP Patent Kokai JP-A-3-58141. For restoration of the port function of the micro-computer, lost by this connection, a port emulation function is accorded to the logic dedicated to the connection.
SUMMARY OF THE DISCLOSURE
However, the above-mentioned conventional technique suffers from the following disadvantages:
The first inconvenience is that, in the integrated circuit proposed in the JP Patent Kokai JP-A-3-58141, the chip in its entirety is increased in circuit scale thus obstructing reduction in size and cost.
The reason is that, since the logic dedicated to connection is provided as an extension on the outer side of the bus/port changeover terminal of the micro-computer, the port function is accorded to both the pre-existing micro-computer and the logic dedicated to the connection.
Specifically, as shown in
FIG. 2
of the above-mentioned JP Patent Kokai JP-A-3-58141, showing an example of the dedicated logic, switch portions (SW
12
and SW
13
of
FIG. 2
of the publication) and a latch (
16
in
FIG. 2
of the publication) are also enclosed in a bus/port changeover terminal (
3
of
FIG. 1
of the publication) provided in the computer of
FIG. 1
of the publication, such that two circuits having the same function are provided in the same chip.
The second drawback is that, for inspecting all portions in a chip in an integrated circuit proposed in the above-mentioned JP Patent Kokai JP-A-3-58141, it is necessary to prepare a test pattern operating in the one-chip mode, that is under a state of controlling the additional logic for user using a CPU in the micro-computer.
The reason is that there exists a portion in the chip that cannot be operated in a mode other than in the one-chip mode. More specifically, a switch of the logic dedicated to connection used for interconnecting the micro-computer side bus and the bus of the additional logic for the user, namely a switch
11
of
FIG. 2
of the JP Patent Kokai JP-A-3-58141, cannot be actuated if in a mode other than in the one-chip mode, such that it is necessary to prepare a dedicated test pattern.
The third drawback is that, if the integrated circuit shown in the second embodiment of the JP Patent Kokai JP-A-3-58141 is actuated in the additional logic test mode, a large number of external terminals of the chip is required.
The reason is that both an interrupt request signal output by the additional logic for the user and an interrupt request signal output by the additional logic for the user need to be input or output as external terminals of the chip.
It is therefore an object of the present invention to provide an integrated circuit of a reduced size and weight by eliminating from the logic dedicated to connection of the conventional integrated circuit the changeover switch or a port signal latch used for realizing the port emulation function to simplify the circuit to reduce the size and weight of the circuit.
It is another object of the present invention to provide an integrated circuit in which an operational test of the logic dedicated to connection, in which a large number of operational steps has been required in preparing a test pattern for operational testing, is facilitated to render it possible to improve productivity and reliability.
It is yet another object of the present invention to provide an integrated circuit in which the number of external terminals of a chip in a shipment test mode of the above-described conventional integrated circuit is decreased to render it possible to reduce the size and weight of the integrated circuit.
For accomplishing the above objects, the present invention provides, in one aspect, an integrated circuit having a micro-computer and an additional logic for the user in one semiconductor chip, including a logic dedicated to connection for interconnecting the micro-computer and the logic for the user, in which the micro-computer has a port circuit connected to an external terminal. The port circuit can input and output data to and from the outside of the chip via the external terminal, the port circuit being connected to a first bus provided in the inside of the micro-computer. The logic dedicated to connection is connected to the first bus provided in the micro-computer and to a second bus for connecting to the additional logic for user. Readout and writing from or to the additional logic for user is enabled via the terminal connected to the port circuit of the micro-computer.
In the integrated circuit of the present invention, the logic dedicated to connection for interconnecting the micro-computer and the additional logic for user has a bus inspection register for inspecting whether or not the second bus for connection to the additional logic for user is operating normally. The bus inspection register is constituted by a bit width which is the same as the data transfer width of the second bus. The bus inspection register is allocated to defined addresses for reading out and writing from or to the micro-computer, and optional data can be written in or read from the micro-computer via the first and second buses.
In the integrated circuit according to a third aspect of the present invention, the additional logic for user has an interrupt request signal to the micro-computer. The dedicated interfacing circuit for interconnecting the micro-computer and the additional logic for user has a circuit for transmitting an interrupt request output by the additional logic for user to the micro-computer and an interrupt request signal inspection register. The interrupt request signal inspection register has a number of bits corresponding to the number of interrupt request signals. An optional value is enabled to be written in each bit of the interrupt request signal inspection register from the micro-computer. There is provided a circuit for transmitting outputs of the respective bits in place of the interrupt request signals to the micro-computer.
The present invention also provided, in another aspect, a semiconductor integrated circuit having a micro-computer and an additional logic for user in one semiconductor chip, wherein a logic dedicated to connection directly connected to an internal bus of the micro-computer is provided between the additional logic for user and the micro-computer. During testing of the additional logic for user, the additional logic for user is freed from control by the CPU of the micro-computer, to make readout and writing from or to the additional logic for user via the internal bus and the logic dedicated to connection from outside using the bus/port changeover terminals of the micro-computer and the readout/writing control signal. Other features are disclosed in the dependent claims which are incorporated herein by reference thereto.


REFERENCES:
patent: 5724603 (1998-03-01), Nishiguchi
patent: 6035431 (2000-03-01), Higashida
patent: 60-258660 (1985-12-01), None
patent: 3-58141 (1991-03-01), None

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