Method to suppress CMOS device latchup and improve interwell...

Details Method to suppress CMOS device latchup and improve interwell... Method to suppress CMOS device latchup and improve interwell...

2000-03-06

2001-05-08

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S220000

Reexamination Certificate

active

06228726

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Fields of the Invention
The present invention relates generally to fabrication of semiconductor devices and more particularly to a process which results in a semiconductor device structure with improved latch-up immunity and interwell isolation.
(2) Description of Prior Art
As complementary field effect transistor (FET) devices are scaled down to have feature sizes below 1.5 micrometers (um) to increase circuit density and improve device performance, several considerations become increasingly important.
One important consideration is latch-up. Latch-up is defined as a high current state which is triggered by certain electrical conditions acting on parasitic bipolar transistors contained in the device structure. Normal circuit control is generally lost when latch-up occurs. The high current generates excessive heat which can become destructive to the device. It is extremely desirable and important to design semiconductor devices with latch-up immunity.
CMOS latch-up is typically caused by parasitic bipolar transistors from the source/drain elements of the CMOS and other device elements such as the N and P wells and the substrate region.
FIG. 1
is a cross sectional view of a prior art semiconductor device which is susceptible to latch-up. The device consists of a N type silicon substrate
10
having a P well
12
and a N well
14
separated by a boundary region
26
. Formed within the P-well
12
are N
+
source/drain regions
16
,
18
and P
+
contact region
28
which is connected to a first voltage source Vss, typically ground. Formed within the N well
14
are P
+
source/drain regions
20
,
22
and N
+
contact region
30
which is connected to a second voltage source V
DD
, typically 3.3 volts (V) or 5.0 V. A shallow trench isolation (STI) structure
24
is formed in a recess between the N and P-well regions, overlaying the boundary region
26
. Gate structures
34
and
36
, comprising of a gate electrodes
38
,
40
and underlying gate oxide layer
42
,
44
complete the essential elements of the N-channel metal oxide semiconductor (NMOS) and P-channel metal oxide semiconductor (PMOS) respectively. It is understood the structures are covered by a passivation layer, typically silicon dioxide (SiO
2
) and appropriately patterned metallurgy, typically Aluminum (Al), for electrical contact. These elements are not shown for clarity.
Latch-up occurs when parasitic bipolar transistors located within the semiconductor device are connected in a positive feedback loop, shown schematically in
FIG. 2. A
parasitic vertical NPN bipolar transistor T
1
is formed by N type source/drain regions
16
,
18
, P-well
12
and substrate
10
. A parasitic lateral NPN bipolar transistor T
2
, which is formed electrically in parallel with vertical NPN bipolar transistor T
1
, is formed by N type source/drain regions
16
,
18
P-well
12
and N-well
14
. A lateral parasitic PNP transistor T
3
is formed by P-type source/drain regions
20
,
22
, N-well
14
and P-well
12
.
FIG. 2
is a schematic diagram of the latchup circuit in semiconductor device. Vertical NPN bipolar transistor T
1
is not shown for purpose of clarity. It is understood that vertical NPN bipolar transistor T
1
is electrically in parallel with lateral NPN bipolar transistor T
2
. As shown in
FIG. 2
, the emitter of T
2
is coupled through a resistor RW
1
to the base of T
2
. The emitter of T
3
is coupled through a resistor RW
2
to the base of T
3
. The collector of T
2
is coupled to the base of T
3
and the collector of T
3
is coupled to the base of T
2
. The emitter of T
3
is effectively connected to Vdd and the emitter of T
2
is effectively connected to Vss, commonly ground.
Latch-up occurs when the voltage drop across resistor RW
2
, and hence the voltage drop between the emitter E and base B of T
3
, is sufficient to turn T
3
on. This causes current to flow between the emitter E and collector C of T
3
. This results in positive feedback producing a voltage drop across resistor RW
1
, and hence a voltage drop between the emitter E and base B of the NPN transistor T
2
. If the voltage drop between the emitter and base of T
2
is sufficient, then T
2
turns on. This causes a current to flow through the emitter and collector of T
2
which increases the current flow through resistor RW
2
increasing the voltage drop between the emitter and base of T
3
. The positive feedback loop continues resulting in latch-up.
By decreasing the values of resistors RW
1
and RW
2
any tendency to forward bias by creating a voltage drop between the emitter and the base of parasitic transistors T
2
and T
3
is reduced and latch-up immunity is improved. Although vertical parasitic NPN bipolar transistor T
1
is not shown for clarity, it is understood that latchup has both a vertical and lateral component. Thus to effectively suppress latchup, both the lateral and vertical elements must be suppressed.
One conventional method to suppress latchup is to form a heavily doped region in the lower portion of P-well
12
. Referring to
FIG. 3
, a mask
50
made of photoresist, is formed overlaying N-well area
14
and partially overlaying the STI structure
24
which is shown as a completed structure filled with SiO
2
. The mask
50
does not extend over the P-well area
12
. The structure is then subject to a high energy implant of P type impurit, shown here as B
+
for Boron. The implant typically takes place with an energy between 60 KeV and 120 KeV. The P type impurity does not pass through mask
50
into the N well region
14
. However, the P type dopant is introduced into a region
32
of P-well
12
, creating a heavily doped region (HD) at a depth below the upper surface of the well and above the upper surface of N type substrate
10
.
Since higher concentrations of dopants improve conductivity, the HD region
32
exhiibits relatively low resistance (high conductivity) which reduces the emitter base resistance and subsequently reduces the tendency for the parasitic vertical NPN transistor T
1
to turn on, thus improving tolerance for latchup. However, the heavily doped region
32
as shown in
FIG. 3
exhibits a lower dopent profile in the boundary region under the STI and does not inhibit lateral latchup under the STI region caused by lateral transistor T
2
and T
3
. As feature size in semiconductor devices are further reduced, lateral latchup becomes increasingly important. Therefore it is desirable to have a method of manufacturing a semiconductor device which inhibits both lateral and vertical latchup.
A similar N+ doping process can be repeated for the N-well area of the device, resulting in a HD layer
46
which has a similar vertical latchup effect for the N-well as HD layer
32
has in the P-well but the heavily doped region
46
as shown in
FIG. 3
also exhibits a lower dopent profile in the boundary region under the STI.
As the impurity concentration in the buried layers
32
,
46
is increased to reduce the resistance of RW
1
, RW
2
, or the depth of the buried layer is reduced, the gate elements
34
,
36
threshold voltage (Vt) is increased, thereby degrading circuit performance. Conversely, as the doping level is decreased, or the depth increased, the effect on the vertical and lateral parasitic bipolar transistors and associated resistors RW
1
and RW
2
is weakened, reducing the resistance to latchup. It is desirable to have a process which improves both lateral and vertical latchup tolerance, and at the same time keep constant or improve transistor threshold voltage tolerance.
Another important consideration in semiconductor technology is interwell isolation, i.e., it is important to prevent current leakage between N-well and P-well. Interwell isolation can further be broken down in to N
+
type source/drain region to N-well isolation, and P
+
type source/drain region to P-well isolation. As feature size in semiconductor devices are further reduced and the N
+
to N well and P
+
to P well spacing decreases, interwell isolation

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